ISQED 2003:
San Jose,
California,
USA
4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA.
IEEE Computer Society 2003, ISBN 0-7695-1881-8 BibTeX
@proceedings{DBLP:conf/isqed/2003,
title = {4th International Symposium on Quality of Electronic Design
(ISQED 2003), 24-26 March 2003, San Jose, CA, USA},
booktitle = {ISQED},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-1881-8},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Design for Yield Optimization and Test
Design for Manufacturing and Yield
IC and Package Co-Design
Design for Reliability
Plenary Session I
Reducing Leakage Currents in VLSI Circuits
SoC Methodology
Testing of SoCs
Design for Manufacturability and Quality
- F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh:
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.
119-124
Electronic Edition (link) BibTeX
- Qi-De Qian, Sheldon X.-D. Tan:
Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis.
125-130
Electronic Edition (link) BibTeX
- Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, David Pinto:
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains.
131-137
Electronic Edition (link) BibTeX
- M. C. Scott, M. O. Peralta, Jo Dale Carothers:
System and Framework for QA of Process Design Kits.
138-143
Electronic Edition (link) BibTeX
- Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Sridhar Subramaniam, Hem Hingarh:
The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange.
144-
Electronic Edition (link) BibTeX
Design Considerations in Advanced Technology
- Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim:
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.
153-158
Electronic Edition (link) BibTeX
- Won Namgoong, Jongrit Lerdworatawee:
Revisiting the Noise Figure Design Metric for Digital Communication Receiver.
159-162
Electronic Edition (link) BibTeX
- N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell:
Benchmarks for Interconnect Parasitic Resistance and Capacitance.
163-
Electronic Edition (link) BibTeX
Interconnect and Substrate Noise
- Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction.
171-176
Electronic Edition (link) BibTeX
- Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Noise-Aware Driver Modeling for Nanometer Technology.
177-182
Electronic Edition (link) BibTeX
- Tom Chen, Amjad Hajjar:
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics.
183-188
Electronic Edition (link) BibTeX
- Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
Modeling Crosstalk Induced Delay.
189-194
Electronic Edition (link) BibTeX
- Hai Lan, Zhiping Yu, Robert W. Dutton:
A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design.
195-
Electronic Edition (link) BibTeX
Impact of New Standards for Design Data Modeling and Manufacturing Interface
Package-Design Interface Challenges
IC and Package Co-Design:
Challenge or Dream?
Power Analysis and Low Power Design
Topics in Device and Interconnect Modeling
Techniques for High-Speed Circuits and Module Generation
Timing and Noise Issues in Physical Design
- Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy.
327-332
Electronic Edition (link) BibTeX
- Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing Inter-Clock Coupling Jitter.
333-338
Electronic Edition (link) BibTeX
- Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.
339-343
Electronic Edition (link) BibTeX
- Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong:
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis.
344-347
Electronic Edition (link) BibTeX
- Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura:
PDL: A New Physical Synthesis Methodology.
348-
Electronic Edition (link) BibTeX
Reliabililty Analysis
- Colin C. McAndrew:
Statistical Modeling for Circuit Simulation.
357-362
Electronic Edition (link) BibTeX
- Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng:
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits.
363-368
Electronic Edition (link) BibTeX
- Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Coupled Simulation of Circuit and Piezoelectric Laminates.
369-372
Electronic Edition (link) BibTeX
- Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong:
Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling.
373-376
Electronic Edition (link) BibTeX
- Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta:
Static Electromigration Analysis for Signal Interconnects.
377-
Electronic Edition (link) BibTeX
Panel Discussion:
Hidden Quality,
Crouching Customer-How Much Does the Quality of EDA Tools Impact Electronic Design?
Interconnect Parasitic Effects
- S. Simon Wong, C. Patrick Yue, Richard Chang, So-Young Kim, Bendik Kleveland, Frank O'Mahony:
On-Chip Interconnect Inductance - Friend or Foe (Invited).
389-394
Electronic Edition (link) BibTeX
- Takashi Sato, Hiroo Masuda:
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.
395-400
Electronic Edition (link) BibTeX
- Soyoung Kim, Yehia Massoud, S. Simon Wong:
On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond.
401-404
Electronic Edition (link) BibTeX
- Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright:
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow.
405-409
Electronic Edition (link) BibTeX
- Li Yang, J. S. Yuan:
Analyzing Internal-Switching Induced Simultaneous Switching Noise.
410-
Electronic Edition (link) BibTeX
Design and Measurement Issues in Testing
Copyright © Sat May 16 23:26:17 2009
by Michael Ley (ley@uni-trier.de)
