DFT 2003:
Boston,
MA,
USA
18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings.
IEEE Computer Society 2003, ISBN 0-7695-2042-1 BibTeX
@proceedings{DBLP:conf/dft/2003,
title = {18th IEEE International Symposium on Defect and Fault-Tolerance
in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA,
Proceedings},
booktitle = {DFT},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-2042-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Yield and Defects
- Xiaopeng Wang, Marco Ottavi, Fabrizio Lombardi:
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs.
3-10
Electronic Edition (link) BibTeX
- Tianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma:
Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip.
11-17
Electronic Edition (link) BibTeX
- Meng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer:
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.
18-25
Electronic Edition (link) BibTeX
- Dirk K. de Vries, Paul L. C. Simon:
Calibration of Open Interconnect Yield Models.
26-33
Electronic Edition (link) BibTeX
- T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri:
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults.
34-
Electronic Edition (link) BibTeX
Optoelectronics
Fault Analysis,
Injection & Simulation
- Cecilia Metra, T. M. Mak, Daniele Rossi:
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.
63-70
Electronic Edition (link) BibTeX
- Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi:
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs.
71-78
Electronic Edition (link) BibTeX
- Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi:
CodSim -- A Combined Delay Fault Simulator.
79-
Electronic Edition (link) BibTeX
Test & Diagnosis
Current Test & Diagnosis
Test Generation & Application
- Hamidreza Hashempour, Fabrizio Lombardi:
ATE-Amenable Test Data Compression with No Cyclic Scan.
151-158
Electronic Edition (link) BibTeX
- Fengming Zhang, Young-Jun Lee, T. Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, S. Max, Phil Perkinson:
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment.
159-166
Electronic Edition (link) BibTeX
- James Wingfield, Jennifer Dworak, M. Ray Mercer:
Function-Based Dynamic Compaction and its Impact on Test Set Sizes.
167-174
Electronic Edition (link) BibTeX
- Xiao Liu, Michael S. Hsiao:
Constrained ATPG for Broadside Transition Testing.
175-
Electronic Edition (link) BibTeX
Scan Design & Test
BIST
Error Correcting Codes
Invited Talk
Analogue & Mixed Signal Test
Defect Tolerance and Testing
- Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi:
Thermal Management of High Performance Microprocessors.
313-319
Electronic Edition (link) BibTeX
- Ying Zhang, Krishnendu Chakrabarty:
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems.
320-327
Electronic Edition (link) BibTeX
- Eiko Sugawara, Masaru Fukushi, Susumu Horiguchi:
Fault Tolerant Multi-Layer Neural Networks with GA Training.
328-335
Electronic Edition (link) BibTeX
- Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.
336-343
Electronic Edition (link) BibTeX
- Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos:
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs.
344-351
Electronic Edition (link) BibTeX
- Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
352-360
Electronic Edition (link) BibTeX
- John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals.
361-368
Electronic Edition (link) BibTeX
- Rafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi:
Fault Tolerant Hopfield Associative Memory on Torus.
369-376
Electronic Edition (link) BibTeX
- B. Nicolescu, P. Peronnard, Raoul Velazco, Yvon Savaria:
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study.
377-384
Electronic Edition (link) BibTeX
- Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng:
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip.
385-392
Electronic Edition (link) BibTeX
- Noh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi:
Regressive Testing for System-on-Chip with Unknown-Good-Yield.
393-400
Electronic Edition (link) BibTeX
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.
401-408
Electronic Edition (link) BibTeX
- Mehdi Baradaran Tahoori:
Application-Dependent Testing of FPGA Interconnects.
409-416
Electronic Edition (link) BibTeX
- Cecilia Metra, Stefano Di Francescantonio, Martin Omaña:
Automatic Modification of Sequential Circuits for Self-Checking Implementation.
417-424
Electronic Edition (link) BibTeX
- Dan Zhao, Shambhu J. Upadhyaya, Martin Margala:
Control Constrained Resource Partitioning for Complex SoCs.
425-432
Electronic Edition (link) BibTeX
- Kartik Mohanram, Nur A. Touba:
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits.
433-
Electronic Edition (link) BibTeX
FPGA & Memory Test
- Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia:
An Integrated Design Approach for Self-Checking FPGAs.
443-450
Electronic Edition (link) BibTeX
- Bai Hong Fang, Nicola Nicolici:
Power-Constrained Embedded Memory BIST Architecture.
451-458
Electronic Edition (link) BibTeX
- Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.
459-466
Electronic Edition (link) BibTeX
- Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker:
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator.
467-474
Electronic Edition (link) BibTeX
- Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott:
An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.
475-
Electronic Edition (link) BibTeX
Design Verification & Synthesis
SoC & Core Test
System Reliability
Fault Tolerance
Soft Errors
Copyright © Sat May 16 23:06:35 2009
by Michael Ley (ley@uni-trier.de)
