Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003.
ACM 2003, ISBN 1-58113-677-3 BibTeX
@proceedings{DBLP:conf/glvlsi/2003,
title = {Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003,
Washington, DC, USA, April 28-29, 2003},
booktitle = {ACM Great Lakes Symposium on VLSI},
publisher = {ACM},
year = {2003},
isbn = {1-58113-677-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
CAD
- Chris Coulston:
Constructing exact octagonal steiner minimal trees.
1-6
Electronic Edition (ACM DL) BibTeX
- Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Bounding the efforts on congestion optimization for physical synthesis.
7-10
Electronic Edition (ACM DL) BibTeX
- Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha:
A comprehensive high-level synthesis system for control-flow intensive behaviors.
11-14
Electronic Edition (ACM DL) BibTeX
VLSI circuits
- Saied Hemati, Amir H. Banihashemi:
Iterative decoding in analog CMOS.
15-20
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- Payam Heydari:
Design issues in low-voltage high-speed current-mode logic buffers.
21-26
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- Magdy A. El-Moursy, Eby G. Friedman:
Optimum wire sizing of RLC interconnect with repeaters.
27-32
Electronic Edition (ACM DL) BibTeX
- Roy Mader, Ivan S. Kourtev:
Reduced dynamic swing domino logic.
33-36
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- Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald:
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.
37-40
Electronic Edition (ACM DL) BibTeX
- Manuel Salim Maza, Mónico Linares Aranda:
Interconnected rings and oscillators as gigahertz clock distribution nets.
41-44
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VLSI in the nanometer era
Poster session 1
- Jia Di, Jiann S. Yuan:
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.
64-67
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- Menahem Lowy, Neal Butler, Rosanne Tinkler:
Low power VLSI sequential circuit architecture using critical race control.
68-71
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- Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier:
A hybrid adiabatic content addressable memory for ultra low-power applications.
72-75
Electronic Edition (ACM DL) BibTeX
- Timm Ostermann, Bernd Deutschmann:
TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits.
76-79
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- Rolf Drechsler, Junhao Shi, Görschwin Fey:
MuTaTe: an efficient design for testability technique for multiplexor based circuits.
80-83
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- Vamsee K. Pamula, Krishnendu Chakrabarty:
Cooling of integrated circuits using droplet-based microfluidics.
84-87
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- Fang Wang, Sofiène Tahar:
Language emptiness checking using MDGs.
88-91
Electronic Edition (ACM DL) BibTeX
- Gianluca Palermo, Cristina Silvano, S. Valsecchi, Vittorio Zaccaria:
A system-level methodology for fast multi-objective design space exploration.
92-95
Electronic Edition (ACM DL) BibTeX
- Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktish Sankaranarayan:
A practical CAD technique for reducing power/ground noise in DSM circuits.
96-99
Electronic Edition (ACM DL) BibTeX
- Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nunez:
RF CMOS circuit optimizing procedure and synthesis tool.
100-103
Electronic Edition (ACM DL) BibTeX
- Charles Chiang, Qing Su, Ching-Shoei Chiang:
Wirelength reduction by using diagonal wire.
104-107
Electronic Edition (ACM DL) BibTeX
- Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-Dong Yang, Sangwoo Kim, Stephan Mueller, Hendrik Mau, Lawrence T. Pileggi:
A fast simulation approach for inductive effects of VLSI interconnects.
108-111
Electronic Edition (ACM DL) BibTeX
- Chang Woo Kang, Soroush Abbaspour, Massoud Pedram:
Buffer sizing for minimum energy-delay product by using an approximating polynomial.
112-115
Electronic Edition (ACM DL) BibTeX
- Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
FORCE: a fast and easy-to-implement variable-ordering heuristic.
116-119
Electronic Edition (ACM DL) BibTeX
- Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura:
Routing methodology for minimizing 1nterconnect energy dissipation.
120-123
Electronic Edition (ACM DL) BibTeX
- Jiwei Chen, Bingxue Shi:
Circuit design of a wide tuning range CMOS VCO with automatic amplitude control.
124-127
Electronic Edition (ACM DL) BibTeX
- Li Yang, J. S. Yuan:
A decoupling technique for CMOS strong-coupled structures.
128-131
Electronic Edition (ACM DL) BibTeX
- Ilias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou:
A custom FPGA for the simulation of gene regulatory networks.
132-135
Electronic Edition (ACM DL) BibTeX
VLSI design
- Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro:
A novel architecture for power maskable arithmetic units.
136-140
Electronic Edition (ACM DL) BibTeX
- John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald, Russell P. Kraft:
3D direct vertical interconnect microprocessors test vehicle.
141-146
Electronic Edition (ACM DL) BibTeX
- Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu:
Zero overhead watermarking technique for FPGA designs.
147-152
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- Geoff Knagge, David Garrett, Sivarama Venkatesan, Chris Nicol:
Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm.
153-156
Electronic Edition (ACM DL) BibTeX
- Rajkiran Gottumukkal, Vijayan K. Asari:
System level design of real time face recognition architecture based on composite PCA.
157-160
Electronic Edition (ACM DL) BibTeX
- Jianhua Gan, Shouli Yan, Jacob A. Abraham:
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array.
161-164
Electronic Edition (ACM DL) BibTeX
VLSI circuits
CAD
- Shyam Ramji, Nagu R. Dhanwada:
Design topology aware physical metrics for placement analysis.
186-191
Electronic Edition (ACM DL) BibTeX
- Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
A novel ultra-fast heuristic for VLSI CAD steiner trees.
192-197
Electronic Edition (ACM DL) BibTeX
- Enrico Macii, Massimo Poncino, Sabino Salerno:
Combining wire swapping and spacing for low-power deep-submicron buses.
198-202
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- Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak:
Clustering based acyclic multi-way partitioning.
203-206
Electronic Edition (ACM DL) BibTeX
- Hua Tang, Hui Zhang, Alex Doboli:
Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing.
207-210
Electronic Edition (ACM DL) BibTeX
- Ameya R. Agnihotri, Patrick H. Madden:
Congestion reduction in traditional and new routing architectures.
211-214
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Low power
Poster session 2
- Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Orthogonal code generator for 3G wireless transceivers.
229-232
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- Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-seog Choi:
54x54-bit radix-4 multiplier based on modified booth algorithm.
233-236
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- Adnan Abdul-Aziz Gutub, Mohammad K. Ibrahim:
Power-time flexible architecture for GF(2k) elliptic curve cryptosystem computation.
237-240
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- Yeshwant Kolla, Yong-Bin Kim, John Carter:
A novel 32-bit scalable multiplier architecture.
241-244
Electronic Edition (ACM DL) BibTeX
- Yanni Chen, Keshab K. Parhi:
High throughput overlapped message passing for low density parity check codes.
245-248
Electronic Edition (ACM DL) BibTeX
- Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe:
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers.
249-252
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- Jung-Lin Yang, Erik Brunvand:
Using dynamic domino circuits in self-timed systems.
253-256
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- Frank Grassert, Dirk Timmermann:
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs.
257-260
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- David Harris, Genevieve Breed, Matt Erler, David Diaz:
Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic.
261-264
Electronic Edition (ACM DL) BibTeX
- Ahmed Emira, Edgar Sánchez-Sinencio:
Variable gain amplifier with offset cancellation.
265-268
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- Atul Maheshwari, Wayne Burleson:
Repeater and current-sensing hybrid circuits for on-chip interconnects.
269-272
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- Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock:
A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.
273-276
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- Yun Cheol Han, Kwang il Kim, Jun Kim, Kwang Sub Yoon:
A dual band CMOS VCO with a balanced duty cycle buffer.
277-280
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- Jiwei Chen, Bingxue Shi:
New approach to CMOS current reference with very low temperature coefficient.
281-284
Electronic Edition (ACM DL) BibTeX
- Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi:
Noise tolerant low voltage XOR-XNOR for fast arithmetic.
285-288
Electronic Edition (ACM DL) BibTeX
Testing
Copyright © Sat May 16 23:13:51 2009
by Michael Ley (ley@uni-trier.de)
