CODES+ISSS 2006: Seoul, Korea

• Wolfgang Mueller, Yves Vanderperren:
  UML and model-driven development for SoC design. 1
  Electronic Edition (ACM DL) BibTeX
• Yoshimi Furukawa, Seiji Kawamura:
  Automotive electronics system, software, and local area network. 2
  Electronic Edition (ACM DL) BibTeX
• Nam Sung Woo:
  Promises and challenges of mobile embedded system: : an industry perspective. 3
  Electronic Edition (ACM DL) BibTeX

HW/SW design exploration for multimedia applications

• Balaji Raman, Samarjit Chakraborty:
  Application-specific workload shaping in multimedia-enabled personal mobile devices. 4-9
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• Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, Gerard J. M. Smit:
  Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure. 10-15
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• Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian:
  Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. 16-21
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Low power scheduling and estimation techniques

• Henrik Lipskoch, Karsten Albers, Frank Slomka:
  Battery discharge aware energy feasibility analysis. 22-27
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• Selim Gurun, Chandra Krintz:
  A run-time, feedback-based energy estimation model For embedded devices. 28-33
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• Puru Choudhary, Diana Marculescu:
  Hardware based frequency/voltage control of voltage frequency island systems. 34-39
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System-level performance issues

• Arne Hamann, Razvan Racu, Rolf Ernst:
  A formal approach to robustness maximization of complex heterogeneous embedded systems. 40-45
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• Ai-Hsin Liu, Robert P. Dick:
  Automatic run-time extraction of communication graphs from multithreaded applications. 46-51
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• Dong-Ik Ko, Shuvra S. Bhattacharyya:
  The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications. 52-57
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Transaction-level modeling and exploration

• Nicola Bombieri, Franco Fummi, Davide Quaglia:
  TLM/network design space exploration for networked embedded systems. 58-63
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• Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski:
  Automatic generation of transaction level models for rapid design space exploration. 64-69
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• Gunar Schirner, Rainer Dömer:
  Accurate yet fast modeling of real-time communication. 70-75
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Architecture and modeling for network-on-chip

• Mohammad Abdullah Al Faruque, Gereon Weiss, Jörg Henkel:
  Bounded arbitration algorithm for QoS-supported on-chip communication. 76-81
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• Seung Eun Lee, Nader Bagherzadeh:
  Increasing the throughput of an adaptive router in network-on-chip (NoC). 82-87
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• Antoine Scherrer, Antoine Fraboulet, Tanguy Risset:
  Automatic phase detection for stochastic on-chip traffic generation. 88-93
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Embedded security and reliability

• Catherine H. Gebotys, Brian A. White:
  Methodology for attack on a Java-based PDA. 94-99
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• Roshan G. Ragel, Sri Parameswaran:
  Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. 100-105
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• Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
  Architectural support for safe software execution on embedded processors. 106-111
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Advanced Techniques for high-level synthesis and physical design

• Tao Xu, Krishnendu Chakrabarty:
  Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips. 112-117
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• Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
  Floorplan driven leakage power aware IP-based SoC design space exploration. 118-123
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• Pilok Lim, Taewhan Kim:
  Thermal-aware high-level synthesis based on network flow method. 124-129
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Design optimization for network-on-chip

• Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli:
  A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. 130-135
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• Krishnan Srinivasan, Karam S. Chatha:
  Layout aware design of mesh based NoC architectures. 136-141
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• Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
  A methodology for design of application specific deadlock-free routing algorithms for NoC systems. 142-147
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Application-specific code optimization

• Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren:
  Retargetable code optimization with SIMD instructions. 148-153
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• Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa:
  Pack instruction generation for media pUsing multi-valued decision diagram. 154-159
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• Carlo Galuzzi, Elena Moscu Panainte, Yana Yankova, Koen Bertels, Stamatis Vassiliadis:
  Automatic selection of application-specific instruction-set extensions. 160-165
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Panel

• Jürgen Teich:
  Are current ESL tools meeting the requirements of advanced embedded systems? 166
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Programming models for multiprocessor systems: from supercomputing programming to multiprocessors on a chip

• Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini:
  SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. 167-172
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• Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito:
  Challenges in exploitation of loop parallelism in embedded applications. 173-180
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• Christopher D. Gill:
  Resource virtualization in real-time CORBA middleware. 181-186
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Simulation, optimization, and acceleration

• Jeffrey Namkung, Dohyung Kim, Rajesh K. Gupta, Igor Kozintsev, Jean-Yves Bouguet, Carole Dulong:
  Phase guided sampling for efficient parallel application simulation. 187-192
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• Wei Qin, Joseph D'Errico, Xinping Zhu:
  A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation. 193-198
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• Wonbok Lee, Kimish Patel, Massoud Pedram:
  B²Sim: : a fast micro-architecture simulator based on basic block characterization. 199-204
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System-level design of MPSoC

• Giovanni Beltrame, Dario Bruschi, Donatella Sciuto, Cristina Silvano:
  Decision-theoretic exploration of multiProcessor platforms. 205-210
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• Hristo Nikolov, Todor Stefanov, Ed F. Deprettere:
  Multi-processor system design with ESPAM. 211-216
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• Seng Lin Shee, Andrea Erdos, Sri Parameswaran:
  Heterogeneous multiprocessor implementations for JPEG: : a case study. 217-222
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System-level optimization

• Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
  Fuzzy decision making in embedded system design. 223-228
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• Yongsoo Joo, Yongseok Choi, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang:
  Demand paging for OneNAND^TM Flash eXecute-in-place. 229-234
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• Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
  Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. 235-240
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Architecture exploration

• Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic:
  Application specific forwarding network and instruction encoding for multi-pipe ASIPs. 241-246
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• Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang:
  A bus architecture for crosstalk elimination in high performance processor design. 247-252
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• Antonis Papanikolaou, T. Grabner, Miguel Miranda, P. Roussel, Francky Catthoor:
  Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations. 253-258
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• Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Brodersen:
  A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. 259-264
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Industry solutions to emerging embedded systems

• Krisztián Flautner:
  Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems. 265
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• Kyung-Ho Kim:
  Key technologies for the next generation wireless communications. 266-269
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Synthesis techniques for accelerators

• Manjunath Kudlur, Kevin Fan, Scott A. Mahlke:
  Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. 270-275
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• Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke:
  Increasing hardware efficiency with multifunction loop accelerators. 276-281
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• Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski:
  Generic netlist representation for system and PE level design exploration. 282-287
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Communication synthesis and analysis for MPSoC

• Simon Schliecker, Matthias Ivers, Rolf Ernst:
  Integrated analysis of communicating tasks in MPSoCs. 288-293
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• Ilya Issenin, Nikil Dutt:
  Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. 294-299
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• Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt:
  System-level power-performance trade-offs in bus matrix communication architecture synthesis. 300-305
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