ISVLSI 2004:
Tampa,
Florida,
USA
2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA.
IEEE Computer Society 2004, ISBN 0-7695-2097-9 BibTeX
@proceedings{DBLP:conf/isvlsi/2004,
title = {2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004),
Emerging Trends in VLSI Systems Design, 19-20 February 2004,
Lafayette, LA, USA},
booktitle = {ISVLSI},
publisher = {IEEE Computer Society},
year = {2004},
isbn = {0-7695-2097-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Regular Papers
Emerging Trends in VLSI Systems
System Level Design
- Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha:
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.
39-45
Electronic Edition (link) BibTeX
- Matthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Fault Tolerant Algorithms for Network-On-Chip Interconnect.
46-51
Electronic Edition (link) BibTeX
- Suryaprasad Jayadevappa, Ravi Shankar, Imad Mahgoub:
A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study.
52-60
Electronic Edition (link) BibTeX
System-on-a-Chip Design
Advanced VLSI Design
- Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit:
Evaluating Alternative Implementations for LDPC Decoder Check Node Function.
77-82
Electronic Edition (link) BibTeX
- Alireza Hodjat, Ingrid Verbauwhede:
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.
83-88
Electronic Edition (link) BibTeX
- Earl E. Swartzlander Jr.:
A Review of Large Parallel Counter Designs.
89-98
Electronic Edition (link) BibTeX
- María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Behavioural Scheduling to Balance the Bit-Level Computational Effort.
99-104
Electronic Edition (link) BibTeX
- Mahadevan Gomathisankaran, Akhilesh Tyagi:
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays.
105-114
Electronic Edition (link) BibTeX
VLSI Circuits and Systems
Low Power VLSI System Design
- Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
Experimental Evaluation of Resonant Clock Distribution.
135-140
Electronic Edition (link) BibTeX
- Peiyi Zhao, Golconda Pradeep Kumar, C. Archana, Magdy A. Bayoumi:
A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.
141-144
Electronic Edition (link) BibTeX
- Joohee Kim, Conrad H. Ziesler:
Fixed-Load Energy Recovery Memory for Low Power.
145-150
Electronic Edition (link) BibTeX
- W. Rhett Davis, Ambarish M. Sule, Hao Hua:
Multi-Parameter Power Minimization of Synthesized Datapaths.
151-157
Electronic Edition (link) BibTeX
- Shu-Shin Chin, Sangjin Hong, Suhwan Kim:
Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.
158-166
Electronic Edition (link) BibTeX
Novel Test Techniques
Physical Design,
Synthesis and Optimization
Poster Papers
- Ghanshyam Nayak, Tejasvi Das, T. M. Rao, P. R. Mukund:
DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal Systems.
207-210
Electronic Edition (link) BibTeX
- Krzysztof Iniewski, Marek Syrzycki:
Low Power 2.5 Gb/s Serializer for SOC Applications.
211-212
Electronic Edition (link) BibTeX
- Jie Long, Jo Yi Foo, Robert J. Weber:
A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCO.
213-214
Electronic Edition (link) BibTeX
- Indrajit Atluri, Tughrul Arslan:
Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation.
215-217
Electronic Edition (link) BibTeX
- Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David F. Cox, Mohammad M. Mojarradi:
A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process.
218-221
Electronic Edition (link) BibTeX
- Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.
222-225
Electronic Edition (link) BibTeX
- Ahmet T. Erdogan, Tughrul Arslan:
Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm.
226-228
Electronic Edition (link) BibTeX
- S. Sukhsawas, Khaled Benkrid:
A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs.
229-232
Electronic Edition (link) BibTeX
- Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao:
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.
233-236
Electronic Edition (link) BibTeX
- Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine:
Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA.
237-238
Electronic Edition (link) BibTeX
- Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song:
Congestion Estimation for 3D Routing.
239-240
Electronic Edition (link) BibTeX
- Hiren D. Patel, Sandeep K. Shukla:
Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models.
241-242
Electronic Edition (link) BibTeX
- Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.
243-248
Electronic Edition (link) BibTeX
- Sangjin Hong, Shu-Shin Chin:
Incorporating Power Reduction Mechanism in Arithmetic Core Design.
249-250
Electronic Edition (link) BibTeX
- Robert D. Kenney, Michael J. Schulte:
Multioperand Decimal Addition.
251-253
Electronic Edition (link) BibTeX
- Abdel Ejnioui, Abdelhalim Alsharqawi:
Pipeline Design Based on Self-Resetting Stage Logic.
254-257
Electronic Edition (link) BibTeX
- Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama:
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.
258-259
Electronic Edition (link) BibTeX
- Chandramouli Gopalakrishnan, Srinivas Katkoori:
Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths.
260-261
Electronic Edition (link) BibTeX
- Arindam Mukherjee:
On the Reduction of Simultaneous Switching in SoCs.
262-263
Electronic Edition (link) BibTeX
- Nattawut Thepayasuwan, Alex Doboli:
OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip.
264-265
Electronic Edition (link) BibTeX
- Peter Zipf, Claude Stötzler, Manfred Glesner:
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture.
266-267
Electronic Edition (link) BibTeX
- Harpreet S. Narula, John G. Harris:
Integrated VLSI Potentiostat for Cyclic Voltammetry in Electrolytic Reactions.
268-270
Electronic Edition (link) BibTeX
- Rajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee:
Handling Data Streams while Compiling C Programs onto Hardware.
271-272
Electronic Edition (link) BibTeX
- Shankar Krithivasan, Michael J. Schulte, John Glossner:
A Subword-Parallel Multiplication and Sum-of-Squares Unit.
273-274
Electronic Edition (link) BibTeX
- Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt:
Hybrid Parallel Counters - Domino and Threshold Logic.
275-276
Electronic Edition (link) BibTeX
- Peter-Michael Seidel, Kenneth Fazel:
Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters.
277-278
Electronic Edition (link) BibTeX
- Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A Memory Aware High Level Synthesis Tool .
279-280
Electronic Edition (link) BibTeX
- Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST.
281-284
Electronic Edition (link) BibTeX
- Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing.
285-288
Electronic Edition (link) BibTeX
- Bassam Shaer:
Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits.
289-290
Electronic Edition (link) BibTeX
- Chandrasekar Rajagopal, Adrián Núñez-Aldana:
CMOS Analog Programmable Logic Array.
291-292
Electronic Edition (link) BibTeX
- Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications .
293-296
Electronic Edition (link) BibTeX
- John D. Thompson, Nandini Karra, Michael J. Schulte:
A 64-bit Decimal Floating-Point Adder.
297-298
Electronic Edition (link) BibTeX
- Nick Iliev, James E. Stine, Nathan Jachimiec:
Parallel Programmable Finite Field GF(2m) Multipliers.
299-302
Electronic Edition (link) BibTeX
- Magesh Sadasivam, Sangjin Hong:
Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow.
303-304
Electronic Edition (link) BibTeX
- Wei Zhang:
Compiler-Directed Data Cache Leakage Reduction.
305-306
Electronic Edition (link) BibTeX
- Venu G. Gudise, Ganesh K. Venayagamoorthy:
FPGA Placement and Routing Using Particle Swarm Optimization.
307-308
Electronic Edition (link) BibTeX
- Abdel Ejnioui, Abdelkader Rhiati:
A Reconfigurable Memory Management Core for Java Applications.
309-312
Electronic Edition (link) BibTeX
- Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha:
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder.
313-316
Electronic Edition (link) BibTeX
- Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi:
FSEL - Selective Predicated Execution for a Configurable DSP Core.
317-320
Electronic Edition (link) BibTeX
- Yuan Li, John G. Harris:
A Spiking Recurrent Neural Network.
321-322
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:34 2009
by Michael Ley (ley@uni-trier.de)