| 2009 |
|---|
| 8 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 111-120 (2009) |
| 2008 |
|---|
| 7 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty,
Richard Kacprowicz:
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs.
DATE 2008: 1103-1106 |
| 6 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.
VTS 2008: 193-198 |
| 5 | EE | Anuja Sehgal,
Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Power-aware SoC test planning for effective utilization of port-scalable testers.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 2007 |
|---|
| 4 | EE | Sudarshan Bahukudumbi,
Sule Ozev,
Krishnendu Chakrabarty,
Vikram Iyengar:
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
ASP-DAC 2007: 823-828 |
| 3 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.
VLSI Design 2007: 459-464 |
| 2 | EE | Sudarshan Bahukudumbi,
Krishnendu Chakrabarty:
Wafer-Level Modular Testing of Core-Based SoCs.
IEEE Trans. VLSI Syst. 15(10): 1144-1154 (2007) |
| 2005 |
|---|
| 1 | EE | Sudarshan Bahukudumbi,
Krishna Bharath:
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.
VLSI Design 2005: 804-807 |
