ICCD 2006:
San Jose,
CA,
USA
24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA.
IEEE 2006 BibTeX
Keynote Presentation
Microarchitecture Optimization
1.2 Timing Analysis
- Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri:
On the Improvement of Statistical Static Timing Analysis.
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- Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
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- Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier:
Reduction of Crosstalk Pessimism using Tendency Graph Approach.
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- Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan:
Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation.
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1.3 Advanced Circuits and Interconnections
- Simon Hollis, Simon W. Moore:
RasP: An Area-efficient, On-chip Network.
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- Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.
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- Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri:
CMOS Comparators for High-Speed and Low-Power Applications.
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- Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara:
Reconfigurable CAM Architecture for Network Search Engines.
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A
- Karl Mohr, Lawrence Clark:
Delay and Area Efficient First-level Cache Soft Error Detection and Correction.
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2.1 Special Session on Nanotechnology - I
3.1 Technology-Aware Design
3.2 Multiprocessors and Systems-on-Chip
- Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar:
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs.
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- Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh:
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.
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- Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad:
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
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- Sean Leventhal, Manoj Franklin:
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors.
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3.3 Robust and Low-Power Design Styles
Banquet - Keynote Speaker
Special Session on Interconnect
5.1 Hardware and Software Scheduling Techniques
5.2 Nanoscale Modeling + Synthesis
5.3 Power Issues in Test
- Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
Electronic Edition (link) BibTeX
- Ho Fai Ko, Nicola Nicolici:
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints.
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- Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker:
Power Droop Testing.
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- Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
Electronic Edition (link) BibTeX
A
Special Session on Hardware Equivalence
7.1 Functional Verification - Advances and Applications
7.2 Application Specific Processing Elements
- Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner:
FPGA Implementation of High Speed FIR Filters Using Add and Shift Method.
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- Osama Al-Khaleel, Christos A. Papachristou, Frank Wolff, Kiamal Z. Pekmestzi:
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.
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- Tinoosh Mohsenin, Bevan M. Baas:
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture.
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- Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi:
An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
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7.3 Physical Design
8.1 Design Techniques and Methods
8.2 System On Chip Design
8.3 Power-Efficient Systems
9.1 Improving test quality
9.2 Architectural Synthesis
10.1 Design Practice
- Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler:
Design and Implementation of the TRIPS Primary Memory System.
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- Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
Implementation and Evaluation of On-Chip Network Architectures.
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- Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang:
Microarchitecture and Performance Analysis of Godson-2 SMT Processor.
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- Satish Narayanasamy, Bruce Carneal, Brad Calder:
Patching Processor Design Errors.
Electronic Edition (link) BibTeX
10.2 Architectural Support for Error Protection
11.1 Special Session on Nanotechnology - II
Copyright © Sat May 16 23:16:37 2009
by Michael Ley (ley@uni-trier.de)
