IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 3

Volume 3, Number 1, March 1995

• Mani B. Srivastava, Miodrag Potkonjak:
  Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput. 2-19
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• Mani B. Srivastava, Robert W. Brodersen:
  System level hardware module generation. 20-35
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• Debabrata Ghosh, S. K. Nandy:
  Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. 36-48
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• Mircea R. Stan, Wayne P. Burleson:
  Bus-invert coding for low-power I/O. 49-58
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• Michael Nicolaidis, Vladimir Castro Alves, Hakim Bederr:
  Testing complex couplings in multiport memories. 59-71
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• Krishnendu Chakrabarty, John P. Hayes:
  Cumulative balance testing of logic circuits. 72-83
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• Jun-Dong Cho, M. Sarrafzadeh:
  A buffer distribution algorithm for high-performance clock net optimization. 84-98
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• Brian S. Cherkauer, Eby G. Friedman:
  A unified design methodology for CMOS tapered buffers. 99-111
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• Steven G. Duvall:
  A practical methodology for the statistical design of complex logic products for performance. 112-123
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• Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee:
  Physical models and algorithms for optoelectronic MCM layout. 124-135
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• M. Agarwala, Poras T. Balsara:
  An architecture for a DSP field-programmable gate array. 136-141
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• Nan-Chi Chou, Chung-Kuan Cheng:
  On general zero-skew clock net construction. 141-146
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• Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu:
  C-testable design techniques for iterative logic arrays. 146-152
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Volume 3, Number 2, June 1995

• Florin Balasa, Francky Catthoor, Hugo De Man:
  Background memory area estimation for multidimensional signal processing systems. 157-172
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• Paul E. Landman, Jan M. Rabaey:
  Architectural power analysis: The dual bit type method. 173-187
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• Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal:
  AVPGEN-A test generator for architecture verification. 188-200
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• R. Vemuri, R. Kalyanaraman:
  Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. 201-214
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• Andrés Takach, Wayne Wolf:
  Scheduling constraint generation for communicating processes. 215-230
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• Brian A. A. Antao, Arthur J. Brodersen:
  ARCHGEN: Automated synthesis of analog systems. 231-244
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• Dan Picker, Ronald D. Fellman:
  A VLSI priority packet queue with inheritance and overwrite. 245-253
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• Hussein M. Alnuweiri, Sadiq M. Sait:
  Efficient network folding techniques for routing permutations in VLSI. 254-263
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• P. Day, J. V. Woods:
  Investigation into micropipeline latch design styles. 264-272
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• Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge:
  Critical paths in circuits with level-sensitive latches. 273-291
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• Vojin G. Oklobdzija, David Villeger:
  Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. 292-301
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• Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
  A practical current sensing technique for I_DDQ testing. 302-310
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• Qingjian Yu, Ernest S. Kuh:
  Exact moment matching model of transmission lines and application to interconnect delay estimation. 311-322
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• Hyunchul Shin, Chunghee Kim:
  Performance-oriented technology mapping for LUT-based FPGA's. 323-327
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• Uming Ko, T. Balsara, Wai Lee:
  Low-power design techniques for high-performance CMOS adders. 327-333
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• Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel:
  Sequential circuit testability enhancement using a nonscan approach. 333-338
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• Shih-Lien Lu:
  Implementation of micropipelines in enable/disable CMOS differential logic. 338-341
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Volume 3, Number 3, September 1995

• M. F. Mar, Robert W. Brodersen:
  A design system for on-chip oversampling A/D interfaces. 345-354
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• Kayhan Küçükçakar, Alice C. Parker:
  A methodology and design tools to support system-level VLSI design. 355-369
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• Chih-Ming Chang, Shih-Lien Lu:
  Design of a static MIMD data flow processor using micropipelines. 370-378
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• Minjoong Rim, Yaw Fann, Rajiv Jain:
  Global scheduling with code-motions for high-level synthesis applications. 379-392
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• Duen-Jeng Wang, Yu Hen Hu:
  Multiprocessor implementation of real-time DSP algorithms. 393-403
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• Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin:
  Power estimation methods for sequential logic circuits. 404-416
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• Brian A. A. Antao, Arthur J. Brodersen:
  Behavioral simulation for analog system design verification. 417-429
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• Weiping Shi, W. Kent Fuchs:
  Optimal interconnect diagnosis of wiring networks. 430-436
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• Shaahin Hessabi, M. Y. Osman, Mohamed I. Elmasry:
  Differential BiCMOS logic circuits: fault characterization and design-for-testability. 437-445
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• Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr:
  Realizing a high measure of confidence for defect level analysis of random testing [VLSI]. 446-450
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• Uming Ko, Poras T. Balsara:
  Short-circuit power driven gate sizing technique for reducing power dissipation. 450-455
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• Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta:
  Performance improvement technique for synchronous circuits realized as LUT-based FPGAs. 455-459
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• Frank Vahid, Daniel D. Gajski:
  Incremental hardware estimation during hardware/software functional partitioning. 459-464
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• A. De Gloria, M. Olivieri:
  Efficient semicustom micropipeline design. 464-469
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Volume 3, Number 4, December 1995

• Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns:
  Placement and routing tools for the Triptych FPGA. 473-482
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• Jie Gong, Daniel D. Gajski, Alexandru Nicolau:
  Performance evaluation for application-specific architectures. 483-490
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• Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns:
  The Triptych FPGA architecture. 491-501
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• William Fornaciari, Fabio Salice:
  A new architecture for the automatic design of custom digital neural network. 502-506
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