ICCD 2008:
Lake Tahoe,
CA,
USA
26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings.
IEEE 2008 BibTeX
Fault and error tolerance
Tree Construction
Formal Verification
Application-Specific Processing Elements
- Jeff Pool, Anselmo Lastra, Montek Singh:
Energy-precision tradeoffs in mobile Graphics Processing Units.
60-67
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- Pankaj Bhagawat, Rajballav Dash, Gwan Choi:
Dynamically reconfigurable soft output MIMO detector.
68-73
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- Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado:
Applying speculation techniques to implement functional units.
74-80
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- Atif Hashmi, Mikko Lipasti:
Accelerating search and recognition with a TCAM functional unit.
81-86
Electronic Edition (link) BibTeX
- Brian J. Hickmann, Michael J. Schulte, Mark A. Erle:
Improved combined binary/decimal fixed-point multipliers.
87-94
Electronic Edition (link) BibTeX
- José Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno:
Architecture implementation of an improved decimal CORDIC method.
95-100
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Clock Distribution
Network-on-Chips
Circuit design
- Kaijian Shi:
Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities.
170-175
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- Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham:
Adaptive SRAM memory for low power and high yield.
176-181
Electronic Edition (link) BibTeX
- Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng:
On-chip high performance signaling using passive compensation.
182-187
Electronic Edition (link) BibTeX
- Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.
188-193
Electronic Edition (link) BibTeX
- Hamed Abrishami, Safar Hatami, Massoud Pedram:
Characterization and design of sequential circuit elements to combat soft error.
194-199
Electronic Edition (link) BibTeX
- Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie:
Comparative analysis of NBTI effects on low power and high performance flip-flops.
200-205
Electronic Edition (link) BibTeX
SoC,
Memory and Analog Testing
Application-Specific Systems
- Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang:
Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA.
240-247
Electronic Edition (link) BibTeX
- Zhibin Xiao, Bevan Baas:
A high-performance parallel CAVLC encoder on a fine-grained many-core system.
248-254
Electronic Edition (link) BibTeX
- Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois:
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor.
255-259
Electronic Edition (link) BibTeX
- Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao:
Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs.
260-265
Electronic Edition (link) BibTeX
- Marc-Andre Daigneault, J. M. Pierre Langlois, Jean-Pierre David:
Application Specific Instruction set processor specialized for block motion estimation.
266-271
Electronic Edition (link) BibTeX
- Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo:
Prototyping a hybrid main memory using a virtual machine monitor.
272-279
Electronic Edition (link) BibTeX
Best Paper Session
- Eren Kursun, Chen-Yong Cher:
Variation-aware thermal characterization and management of multi-core architectures.
280-285
Electronic Edition (link) BibTeX
- Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai:
Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.
286-293
Electronic Edition (link) BibTeX
- David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Analysis and minimization of practical energy in 45nm subthreshold logic circuits.
294-300
Electronic Edition (link) BibTeX
- Kai-Chiang Wu, Diana Marculescu:
Power-aware soft error hardening via selective voltage scaling.
301-306
Electronic Edition (link) BibTeX
- Ilya Wagner, Valeria Bertacco:
Reversi: Post-silicon validation system for modern microprocessors.
307-314
Electronic Edition (link) BibTeX
VLSI signal processing
Simulation and Reliability
- John P. Grossman, John K. Salmon, Richard C. Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw:
Hierarchical simulation-based verification of Anton, a special-purpose parallel machine.
340-347
Electronic Edition (link) BibTeX
- Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
Post-silicon verification for cache coherence.
348-355
Electronic Edition (link) BibTeX
- Christian Hochberger, Alexander Weiss:
Acquiring an exhaustive, continuous and real-time trace from SoCs.
356-362
Electronic Edition (link) BibTeX
- Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin:
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.
363-370
Electronic Edition (link) BibTeX
Multi-Threaded and Multi-Core Architectures
- Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer:
Exploiting spare resources of in-order SMT processors executing hard real-time threads.
371-376
Electronic Edition (link) BibTeX
- Carsten Gremzow:
Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design.
377-383
Electronic Edition (link) BibTeX
- Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song:
A simple latency tolerant processor.
384-389
Electronic Edition (link) BibTeX
- Marius Grannæs, Magnus Jahre, Lasse Natvig:
Low-cost open-page prefetch scheduling in chip multiprocessors.
390-396
Electronic Edition (link) BibTeX
- Arun A. Nair, Lizy K. John:
Simulation points for SPEC CPU 2006.
397-403
Electronic Edition (link) BibTeX
VLSI Arithmetic
- Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Synthesis of parallel prefix adders considering switching activities.
404-409
Electronic Edition (link) BibTeX
- Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev:
Conversion driven design of binary to mixed radix circuits.
410-415
Electronic Edition (link) BibTeX
- Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Systematic design of high-radix Montgomery multipliers for RSA processors.
416-421
Electronic Edition (link) BibTeX
- Shai Erez, Guy Even:
An improved micro-architecture for function approximation using piecewise quadratic interpolation.
422-426
Electronic Edition (link) BibTeX
- Hani Saleh, Earl E. Swartzlander Jr.:
A floating-point fused dot-product unit.
427-431
Electronic Edition (link) BibTeX
Modelling,
Estimation and Simulation
- Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran:
Chip level thermal profile estimation using on-chip temperature sensors.
432-437
Electronic Edition (link) BibTeX
- Shilpa Bhoj, Dinesh Bhatia:
Early stage FPGA interconnect leakage power estimation.
438-443
Electronic Edition (link) BibTeX
- Aswin Sreedhar, Sandip Kundu:
Modeling and analysis of non-rectangular transistors caused by lithographic distortions.
444-449
Electronic Edition (link) BibTeX
- Dimitris Bountas, Georgios Stamoulis, Nestoras E. Evmorfopoulos:
A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions.
450-456
Electronic Edition (link) BibTeX
- Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang:
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.
457-462
Electronic Edition (link) BibTeX
Multi-processor and Multi-core Systems
Emerging Techniques
- Juan Carlos Martinez Santos, Yunsi Fei:
Leveraging speculative architectures for run-time program validation.
498-505
Electronic Edition (link) BibTeX
- Michael T. Niemier, Xiaobo Sharon Hu, Aaron Dingler, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod:
Bridging the gap between nanomagnetic devices and circuits.
506-513
Electronic Edition (link) BibTeX
- Christopher Nitta, Matthew Farrens:
Techniques for increasing effective data bandwidth.
514-519
Electronic Edition (link) BibTeX
- Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Kim, Seungryoul Maeng:
RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache.
520-525
Electronic Edition (link) BibTeX
- Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes.
526-531
Electronic Edition (link) BibTeX
Timing
- Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Timing analysis considering IR drop waveforms in power gating designs.
532-537
Electronic Edition (link) BibTeX
- Sz-Cheng Huang, Jie-Hong Roland Jiang:
A dynamic accuracy-refinement approach to timing-driven technology mapping.
538-543
Electronic Edition (link) BibTeX
- Veerapaneni Nagbhushan, C. Y. Roger Chen:
Modeling and reduction of complex timing constraints in high performance digital circuits.
544-550
Electronic Edition (link) BibTeX
- Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi:
SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.
551-556
Electronic Edition (link) BibTeX
- Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz:
Is there always performance overhead for regular fabric?
557-562
Electronic Edition (link) BibTeX
Energy-Efficiency and Security in Processor Designs
- Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot:
Adaptive techniques for leakage power management in L2 cache peripheral circuits.
563-569
Electronic Edition (link) BibTeX
- Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte:
Energy-aware opcode design.
570-576
Electronic Edition (link) BibTeX
- Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhijie Jerry Shi:
Making register file resistant to power analysis attacks.
577-582
Electronic Edition (link) BibTeX
- Shrirang M. Yardi, Michael S. Hsiao:
Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads.
583-590
Electronic Edition (link) BibTeX
- Christos Strydis:
Suitable cache organizations for a novel biomedical implant processor.
591-598
Electronic Edition (link) BibTeX
- Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera:
Issue system protection mechanisms.
599-604
Electronic Edition (link) BibTeX
Low power
- Liang Di, Mateja Putic, John Lach, Benton H. Calhoun:
Power switch characterization for fine-grained dynamic voltage scaling.
605-611
Electronic Edition (link) BibTeX
- Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000.
612-617
Electronic Edition (link) BibTeX
- Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.
618-625
Electronic Edition (link) BibTeX
- Steven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil:
Energy-delay tradeoffs in 32-bit static shifter designs.
626-632
Electronic Edition (link) BibTeX
- Baoxian Zhao, Hakan Aydin, Dakai Zhu:
Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems.
633-639
Electronic Edition (link) BibTeX
Tools and Methodologies
Cache Architectures
- Jason Zebchuk, Srihari Makineni, Donald Newell:
Re-examining cache replacement policies.
671-678
Electronic Edition (link) BibTeX
- Chuanjun Zhang, Bing Xue:
Two dimensional highly associative level-two cache design.
679-684
Electronic Edition (link) BibTeX
- Chungsoo Lim, Gregory T. Byrd:
Exploiting producer patterns and L2 cache for timely dependence-based prefetching.
685-692
Electronic Edition (link) BibTeX
- Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin:
Ring data location prediction scheme for Non-Uniform Cache Architectures.
693-698
Electronic Edition (link) BibTeX
- Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum:
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
699-706
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:16:36 2009
by Michael Ley (ley@uni-trier.de)
