| 1999 |
|---|
| 11 | EE | Teruhiko Yamada,
Toshinori Kotake,
Hiroshi Takahashi,
Koji Yamazaki:
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.
Asian Test Symposium 1999: 269-274 |
| 1998 |
|---|
| 10 | EE | Teruhiko Yamada,
Tsuneto Hanashima,
Yasuhiro Suemori,
Masaaki Maezawa:
On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.
Asian Test Symposium 1998: 222-227 |
| 9 | | Teruhiko Yamada:
1997 Asian Test Symposium.
IEEE Design & Test of Computers 15(1): 6- (1998) |
| 1997 |
|---|
| 8 | EE | Koji Yamazaki,
Teruhiko Yamada:
An approach to diagnose logical faults in partially observable sequential circuits.
Asian Test Symposium 1997: 168-173 |
| 1996 |
|---|
| 7 | EE | Teruhiko Yamada,
Tsuyoshi Sasaki:
On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family.
Asian Test Symposium 1996: 189- |
| 1995 |
|---|
| 6 | EE | Teruhiko Yamada,
Koji Yamazaki,
Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits.
Asian Test Symposium 1995: 65-70 |
| 5 | | Teruhiko Yamada:
Accelerating the Pace of R&D in Asia.
IEEE Design & Test of Computers 12(3): 12-13 (1995) |
| 1985 |
|---|
| 4 | EE | Yoshiyuki Koseki,
Teruhiko Yamada:
PLAYER: a PLA design system for VLSI's.
DAC 1985: 766-769 |
| 1984 |
|---|
| 3 | | Teruhiko Yamada,
Takashi Nanya:
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults.
IEEE Trans. Computers 33(8): 758-761 (1984) |
| 1983 |
|---|
| 2 | | Teruhiko Yamada:
Syndrome-Testable Design of Programmable Logic Arrays.
ITC 1983: 453-459 |
| 1 | | Teruhiko Yamada,
Takashi Nanya:
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".
IEEE Trans. Computers 32(5): 511-512 (1983) |
