2007 |
21 | EE | K. W. Sum,
Paul Y. S. Cheung:
Boundary vector field for parametric active contours.
Pattern Recognition 40(6): 1635-1645 (2007) |
2005 |
20 | EE | Ronald H. Y. Chung,
N. H. C. Yung,
Paul Y. S. Cheung:
An Efficient Parameterless Quadrilateral-Based Image Segmentation Method.
IEEE Trans. Pattern Anal. Mach. Intell. 27(9): 1446-1458 (2005) |
2002 |
19 | EE | Hing Y. Chung,
Nelson Hon Ching Yung,
Paul Y. S. Cheung:
A novel quadrilateral-based tracking method.
ICARCV 2002: 282-285 |
18 | EE | K. K. Leung,
N. H. C. Yung,
Paul Y. S. Cheung:
Novel Neighborhood Search for Multiprocessor Scheduling with Pipelining.
J. Parallel Distrib. Comput. 62(1): 85-110 (2002) |
2001 |
17 | EE | Wai-Sum Lin,
Rynson W. H. Lau,
Kai Hwang,
Xiaola Lin,
Paul Y. S. Cheung:
Adaptive Parallel Rendering on Multiprocessors and Workstation Clusters.
IEEE Trans. Parallel Distrib. Syst. 12(3): 241-258 (2001) |
16 | EE | Yuzhong Sun,
Paul Y. S. Cheung,
Xiaola Lin:
Barrier Synchronization on Wormhole-Routed Networks.
IEEE Trans. Parallel Distrib. Syst. 12(6): 583-597 (2001) |
15 | EE | Xiaowei Li,
Paul Y. S. Cheung:
A Loop-Based Apparatus for At-Speed Self-Testing.
J. Comput. Sci. Technol. 16(3): 278-285 (2001) |
2000 |
14 | EE | Yuzhong Sun,
Paul Y. S. Cheung,
Xiaola Lin:
Recursive Cube of Rings: A New Topology for Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst. 11(3): 275-286 (2000) |
13 | EE | Xiaowei Li,
Paul Y. S. Cheung:
High Level Synthesis for Loop-Based BIST.
J. Comput. Sci. Technol. 15(4): 338-345 (2000) |
12 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Exploiting Deterministic TPG for Path Delay Testing.
J. Comput. Sci. Technol. 15(5): 472-479 (2000) |
11 | EE | Xiaowei Li,
Paul Y. S. Cheung,
Hideo Fujiwara:
LFSR-Based Deterministic TPG for Two-Pattern Testing.
J. Electronic Testing 16(5): 419-426 (2000) |
1999 |
10 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Data Path Synthesis for BIST with Low Area Overhead.
ASP-DAC 1999: 275-278 |
9 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Exploiting Test Resource Optimization in Data Path Synthesis for BIST.
Great Lakes Symposium on VLSI 1999: 342-343 |
8 | EE | Xiaowei Li,
Paul Y. S. Cheung:
An approach to behavioral synthesis for loop-based BIST.
ISCAS (6) 1999: 374-377 |
7 | EE | Paul Y. S. Cheung,
S. K. Yeung,
W. L. Ko:
A new optimization model for VLSI placement algorithms.
ISCAS (6) 1999: 398-403 |
6 | | Yuzhong Sun,
Paul Y. S. Cheung,
Xiaola Lin:
Asynchronous Acknowledged All-to-All Personalized Exchange with Minimum Startup in 2D/3D Meshes.
PDPTA 1999: 2259-2265 |
1998 |
5 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Exploiting BIST Approach for Two-Pattern Testing.
Asian Test Symposium 1998: 424-429 |
4 | EE | Sam Lin,
Rynson W. H. Lau,
Xiaola Lin,
Paul Y. S. Cheung:
An Anti-Aliasing Method for Parallel Rendering.
Computer Graphics International 1998: 228- |
3 | EE | Xiaowei Li,
Paul Y. S. Cheung:
High-Level BIST Synthesis for Delay Testing.
DFT 1998: 318- |
2 | | Hing Y. Chung,
Paul Y. S. Cheung,
N. H. C. Yung:
Adaptive Search Center Non-Linear Three Step Search.
ICIP (2) 1998: 191-194 |
1 | EE | Yuzhong Sun,
Paul Y. S. Cheung,
Xiaola Lin,
Keqin Li:
Fault Tolerant All-to-All Broadcast in General Interconnection Networks.
ICPADS 1998: 240-247 |