| 2008 |
|---|
| 9 | EE | Masaru Fujita,
Haruhiko Takase,
Hidehiko Kita,
Terumine Hayashi:
Shape of error surfaces in SpikeProp.
IJCNN 2008: 840-844 |
| 2007 |
|---|
| 8 | | Kazutaka Noro,
Haruhiko Takase,
Hidehiko Kita,
Terumine Hayashi,
Naoki Morita:
Descriptive Answer Clustering System for Immediate Feedback.
ICCE 2007: 37-40 |
| 7 | EE | Haruhiko Takase,
Masahiko Masahiko,
Hidehiko Kita,
Terumine Hayashi:
Enhancing both generalization and fault tolerance of multilayer neural networks.
IJCNN 2007: 1429-1433 |
| 2005 |
|---|
| 6 | EE | Terumine Hayashi,
Haruna Yoshioka,
Tsuyoshi Shinogi,
Hidehiko Kita,
Haruhiko Takase:
On Test Data Compression Using Selective Don't-Care Identification.
J. Comput. Sci. Technol. 20(2): 210-215 (2005) |
| 2004 |
|---|
| 5 | EE | Terumine Hayashi,
Haruna Yoshioka,
Tsuyoshi Shinogi,
Hidehiko Kita,
Haruhiko Takase:
Test data compression technique using selective don't-care identification.
ASP-DAC 2004: 230-233 |
| 2001 |
|---|
| 4 | EE | Junzhi Sang,
Tsuyoshi Shinogi,
Haruhiko Takase,
Hidehiko Kita,
Terumine Hayashi:
An enhanced fault model for high defect coverage.
Systems and Computers in Japan 32(6): 36-44 (2001) |
| 2000 |
|---|
| 3 | EE | Haruhiko Takase,
Tsuyoshi Shinogi,
Terumine Hayashi,
Hidehiko Kita:
Evaluation Function for Fault Tolerant Multi-Layer Neural Networks.
IJCNN (3) 2000: 521-526 |
| 1999 |
|---|
| 2 | EE | Kai Zhang,
Tsuyoshi Shinogi,
Haruhiko Takase,
Terumine Hayashi:
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition.
ASP-DAC 1999: 291-294 |
| 1998 |
|---|
| 1 | EE | Junzhi Sang,
Tsuyoshi Shinogi,
Haruhiko Takase,
Terumine Hayashi:
On a Logical Fault Model H1SGLF for Enhancing Defect Coverage.
Asian Test Symposium 1998: 102-107 |
