| 2000 |
|---|
| 8 | EE | Bechir Ayari,
Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment.
J. Electronic Testing 16(5): 409-418 (2000) |
| 1998 |
|---|
| 7 | EE | Bechir Ayari,
Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment.
Asian Test Symposium 1998: 21-26 |
| 1996 |
|---|
| 6 | EE | Naim Ben Hamida,
Bechir Ayari,
Bozena Kaminska:
Testing of embedded A/D converters in mixed-signal circuit.
ICCD 1996: 135-136 |
| 1995 |
|---|
| 5 | | Samir Lejmi,
Bozena Kaminska,
Bechir Ayari:
Retiming for BIST-Sequential Circuits.
ISCAS 1995: 1740-1743 |
| 4 | | Bechir Ayari,
Bozena Kaminska:
BDD-FTEST: Fast, Backtrack-Free Test Generator Based on Binary Decision Diagram Representation.
ISCAS 1995: 2132-2135 |
| 3 | | Samir Lejmi,
Bozena Kaminska,
Bechir Ayari:
Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits.
ITC 1995: 683-692 |
| 2 | EE | Samir Lejmi,
Bozena Kaminska,
Bechir Ayari:
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.
VTS 1995: 434-439 |
| 1994 |
|---|
| 1 | EE | Bechir Ayari,
Bozena Kaminska:
A new dynamic test vector compaction for automatic test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 353-358 (1994) |
