17. PATMOS 2007:
Gothenburg,
Sweden
Nadine Azémard, Lars J. Svensson (Eds.):
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings.
Lecture Notes in Computer Science 4644 Springer 2007, ISBN 978-3-540-74441-2 BibTeX
High-Level Design (1)
Low Power Design Techniques
- Ming-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li:
Template Vertical Dictionary-Based Program Compression Scheme on the TTA.
43-52
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- Delong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev:
Asynchronous Functional Coupling for Low Power Sensor Network Processors.
53-63
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- Noureddine Chabini:
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs.
64-74
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- Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt:
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports.
75-85
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- Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li:
The Design and Implementation of a Power Efficient Embedded SRAM.
86-96
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Statistical Static Timing Analysis
- Björn Lipka, Ulrich Kleine:
Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADIN.
97-106
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- Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling Time Minimization of Operational Amplifiers.
107-116
Electronic Edition (link) BibTeX
- Cosmin Popa:
Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs.
117-124
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- Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula:
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations.
125-137
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- V. Migairou, Robin Wilson, S. Engels, Zequin Wu, Nadine Azémard, Philippe Maurine:
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.
138-147
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- Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang:
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.
148-159
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Power Modeling and Optimization
- Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.
160-170
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- Marko Hoyer, Domenik Helms, Wolfgang Nebel:
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components.
171-180
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- Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija:
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology.
181-190
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- C. R. Parthasarathy, A. Bravaix, C. Guérin, M. Denais, V. Huard:
Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation.
191-200
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Low Power Routing Optimization
- Davide Pandini, Guido A. Repetto, Vincenzo Sinisi:
Clock Distribution Techniques for Low-EMI Design.
201-210
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- Mini Nanua, David Blaauw:
Crosstalk Waveform Modeling Using Wave Fitting.
211-221
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- Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu:
Weakness Identification for Effective Repair of Power Distribution Network.
222-231
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- Prassanna Sithambaram, Alberto Macii, Enrico Macii:
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.
232-241
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- Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner:
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.
242-254
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High Level Design (2)
- Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh:
Soft Error-Aware Power Optimization Using Gate Sizing.
255-267
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- Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger:
Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices.
268-277
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- Sven Rosinger, Domenik Helms, Wolfgang Nebel:
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating.
278-287
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- Allan Crone, Gabriel Chidolue:
Functional Verification of Low Power Designs at RTL.
288-299
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- Zoltán Herczeg, Ákos Kiss, Daniel Schmidt, Norbert Wehn, Tibor Gyimóthy:
XEEMU: An Improved XScale Power Simulator.
300-309
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Security and Asynchronous Design
Low Power Applications
- Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform.
352-362
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- Hendrik Eeckhaut, Harald Devos, Dirk Stroobandt:
The Energy Scalability of Wavelet-Based, Scalable Video Decoding.
363-372
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- Miguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
373-383
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Poster1 - Modeling and Optimization
- Toshinori Sato, Yuji Kunitake:
Exploiting Input Variations for Energy Reduction.
384-393
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- Alin Razafindraibe, Philippe Maurine:
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates.
394-403
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- David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Static Power Consumption in CMOS Gates Using Independent Bodies.
404-412
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- Fabrice Guigues, Edith Kussener, Benjamin Duval, Hervé Barthélemy:
Moderate Inversion: Highlights for Low Voltage Design.
413-422
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- Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui:
On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems.
423-432
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- Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest:
Semi Custom Design: A Case Study on SIMD Shufflers.
433-442
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Poster 2 - High Level Design
- Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh:
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models.
443-452
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- Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki:
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
453-462
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- Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram:
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits.
463-473
Electronic Edition (link) BibTeX
- Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.
474-484
Electronic Edition (link) BibTeX
- Christophe Lucarz, Marco Mattavelli:
A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning.
485-494
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- Henrik Lipskoch, Karsten Albers, Frank Slomka:
Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems.
495-504
Electronic Edition (link) BibTeX
- Nikolas Kroupis, Dimitrios Soudris:
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate.
505-515
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Poster 3 - Low Power Techniques and Applications
- Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti:
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
516-525
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- Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg:
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data.
526-535
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- Jon Alfredsson, Snorre Aunet:
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.
536-545
Electronic Edition (link) BibTeX
- Charalambos Basetas, Ioannis Kouretas, Vassilis Paliouras:
Low-Power Digital Filtering Based on the Logarithmic Number System.
546-555
Electronic Edition (link) BibTeX
- Sylvain Miermont, Pascal Vivet, Marc Renaudin:
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling.
556-565
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- Henrik Eriksson:
Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers.
566-575
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Keynotes
Industrial Session - Design Challenges in Real-Life Projects
Copyright © Sat May 16 23:32:38 2009
by Michael Ley (ley@uni-trier.de)
