dblp.uni-trier.de www.uni-trier.de

17. PATMOS 2007: Gothenburg, Sweden

Nadine Azémard, Lars J. Svensson (Eds.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Lecture Notes in Computer Science 4644 Springer 2007, ISBN 978-3-540-74441-2 BibTeX

High-Level Design (1)

Low Power Design Techniques

Statistical Static Timing Analysis

Power Modeling and Optimization

Low Power Routing Optimization

High Level Design (2)

Security and Asynchronous Design

Low Power Applications

Poster1 - Modeling and Optimization

Poster 2 - High Level Design

Poster 3 - Low Power Techniques and Applications


Industrial Session - Design Challenges in Real-Life Projects

Copyright © Sat May 16 23:32:38 2009 by Michael Ley (ley@uni-trier.de)