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Shidhartha Das

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2008
6EEGanesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David Bull: DVFS in loop accelerators using BLADES. DAC 2008: 894-897
2004
5EESeokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310
4EESeokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324
3EEDan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)
2003
2EEShidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
1EEDan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18

Coauthor Index

1Kanak Agarwal [2]
2Todd M. Austin [1] [3] [4] [5]
3Valeria Bertacco [5]
4David Blaauw (David T. Blaauw) [1] [2] [3] [4] [5]
5David Bull [6]
6Ganesh S. Dasika [6]
7Dan Ernst [1] [3]
8Kevin Fan [6]
9Krisztián Flautner [1] [3]
10Nam Sung Kim [1] [3]
11Seokwoo Lee [3] [4] [5]
12Scott A. Mahlke [6]
13Trevor N. Mudge [1] [3] [4] [5]
14Sanjay Pant [1]
15Toan Pham [1] [4]
16Rajeev R. Rao [1]
17Dennis Sylvester [2]
18Conrad H. Ziesler [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)