| 1993 |
|---|
| 8 | EE | Dah-Cherng Yuan,
Lawrence T. Pillage,
Joseph T. Rahmeh:
Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation.
DAC 1993: 367-372 |
| 1992 |
|---|
| 7 | | Shien-Tai Pan,
Kimming So,
Joseph T. Rahmeh:
Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation.
ASPLOS 1992: 76-84 |
| 1991 |
|---|
| 6 | | Sankaran Karthik,
Indira de Souza,
Joseph T. Rahmeh,
Jacob A. Abraham:
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter.
ICCD 1991: 393-396 |
| 1990 |
|---|
| 5 | | Prithviraj Banerjee,
Joseph T. Rahmeh,
Craig B. Stunkel,
V. S. S. Nair,
Kaushik Roy,
Vijay Balasubramanian,
Jacob A. Abraham:
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor.
IEEE Trans. Computers 39(9): 1132-1145 (1990) |
| 4 | EE | Daniel G. Saab,
Robert B. Mueller-Thuns,
David Blaauw,
Joseph T. Rahmeh,
Jacob A. Abraham:
Hierarchical multi-level fault simulation of large systems.
J. Electronic Testing 1(2): 139-149 (1990) |
| 1989 |
|---|
| 3 | EE | David Blaauw,
Daniel G. Saab,
Robert B. Mueller-Thuns,
Jacob A. Abraham,
Joseph T. Rahmeh:
Automatic Generation of Behavioral Models from Switch-Level Descriptions.
DAC 1989: 179-184 |
| 1986 |
|---|
| 2 | EE | Hsi-Ching Shih,
Joseph T. Rahmeh,
Jacob A. Abraham:
FAUST: An MOS Fault Simulator with Timing Information.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 557-563 (1986) |
| 1985 |
|---|
| 1 | | Peter Y.-T. Hsu,
Joseph T. Rahmeh,
Edward S. Davidson,
Jacob A. Abraham:
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology.
ISCA 1985: 28-35 |
