Volume 24,
Number 1,
January/February
Editor-in-Chief's Message
Micro Law
Hot Interconnects 11
- J. Bryan Lyles:
Guest Editor's Introduction: Hot Interconnects 11 - Solving Network Bottlenecks.
8-9
Electronic Edition (link) BibTeX
- Justin Gus Hurwitz, Wu-chun Feng:
End-to-End Performance of 10-Gigabit Ethernet on Commodity Systems.
10-22
Electronic Edition (link) BibTeX
- Greg J. Regnier, Dave B. Minturn, Gary L. McAlpine, Vikram A. Saletore, Annie Foong:
ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine.
24-31
Electronic Edition (link) BibTeX
- Andrew Lines:
Asynchronous Interconnect for Synchronous SoC Design.
32-41
Electronic Edition (link) BibTeX
- Jiuxing Liu, B. Chandrasekaran, Weikuan Yu, Jiesheng Wu, Darius Buntinas, Sushmitha P. Kini, Dhabaleswar K. Panda, Pete Wyckoff:
Microbenchmark Performance Comparison of High-Speed Cluster Interconnects.
42-51
Electronic Edition (link) BibTeX
- Sarang Dharmapurikar, Praveen Krishnamurthy, Todd S. Sproull, John W. Lockwood:
Deep Packet Inspection using Parallel Bloom Filters.
52-61
Electronic Edition (link) BibTeX
- David V. Schuehler, James Moscola, John W. Lockwood:
Architecture for a Hardware-Based, TCP/IP Content-Processing System.
62-69
Electronic Edition (link) BibTeX
Micro Review
Micro Economics
Parting Thoughts
Volume 24,
Number 2,
March/April 2004
Editor-in-Chief's Message
Micro Law
Hot Chips 15
- Michael J. Flynn, Pradeep K. Dubey:
Guest Editors' Introduction: Hot Chips 15--Scaling the Silicon Mountain.
7-9
Electronic Edition (link) BibTeX
- Stefan Rusu, Harry Muljono, Brian S. Cherkauer:
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.
10-18
Electronic Edition (link) BibTeX
- Sanjiv Kapil, Harlan McGhan, Jesse Lawrendra:
A Chip Multithreaded Processor for Network-Facing Workloads.
20-30
Electronic Edition (link) BibTeX
- Deepu Talla, Ching-Yu Hung, Raj Talluri, Frank Brill, David Smith, David Brier, Bruce Xiong, Derek Huynh:
Anatomy of a Portable Digital Mediaprocessor.
32-39
Electronic Edition (link) BibTeX
- Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler:
IBM Power5 Chip: A Dual-Core Multithreaded Processor.
40-47
Electronic Edition (link) BibTeX
- Uri Cummings:
PivotPoint: Clockless Crossbar Switch for High-Performance Embedded Systems.
48-59
Electronic Edition (link) BibTeX
- V. C. Ravikumar, Rabi N. Mahapatra:
TCAM Architecture for IP Lookup Using Prefix Properties.
60-69
Electronic Edition (link) BibTeX
Micro Economics
News
Parting Thoughts
Volume 24,
Number 3,
May/June 2004
Editor-in-Chief's Message
Micro Law
Application-Specific Processors
Micro Economics
Micro Review
Micro News
Volume 24,
Number 4,
July/August 2004
Editor-in-Chief's Message
Micro Law
Application-Specific Processors
- Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete:
Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems.
8-9
Electronic Edition (link) BibTeX
- Alexander G. Dean:
Efficient Real-Time Fine-Grained Concurrency on Low-Cost Microcontrollers.
10-22
Electronic Edition (link) BibTeX
- Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández:
QoS for High-Performance SMT Processors in Embedded Systems.
24-31
Electronic Edition (link) BibTeX
- Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough:
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1.
33-41
Electronic Edition (link) BibTeX
- David L. Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden:
Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link.
42-53
Electronic Edition (link) BibTeX
- Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner:
Design Space Exploration for Real-Time Embedded Stream Processors.
54-66
Electronic Edition (link) BibTeX
- Andreas Krall, Ivan Pryanishnikov, Ulrich Hirnschrott, Christian Panis:
xDSPcore: A Compiler-Based Configurable Digital Signal Processor.
67-78
Electronic Edition (link) BibTeX
Micro Economics
Micro News
Micro Review
Volume 24,
Number 5,
September-October 2004
Editor-in-Chief's Message
Micro Law
Network Processors
- Ioannis Papaefstathiou, Nikos A. Nikolaou, Bharat T. Doshi, Eric Grosse:
Guest Editors' Introduction: Network Processors for Future High-End Systems and Applications.
7-9
Electronic Edition (link) BibTeX
- Jakob Carlström, Thomas Boden:
Synchronous Dataflow Architecture for Network Processors.
10-18
Electronic Edition (link) BibTeX
- Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos:
PRO3: A Hybrid NPU Architecture.
20-33
Electronic Edition (link) BibTeX
- Yan Luo, Jun Yang, Laxmi N. Bhuyan, Li Zhao:
NePSim: A Network Processor Simulator with a Power Evaluation Framework.
34-44
Electronic Edition (link) BibTeX
- Niraj Shah, William Plishker, Kaushik Ravindran, Kurt Keutzer:
NP-Click: A Productive Software Development Approach for Network Processors.
45-54
Electronic Edition (link) BibTeX
- Zhangxi Tan, Chuang Lin, Hao Yin, Bo Li:
Optimization and Benchmark of Cryptographic Algorithms on Network Processors.
55-69
Electronic Edition (link) BibTeX
- Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough:
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2.
70-78
Electronic Edition (link) BibTeX
Micro Economics
Micro Review
Volume 24,
Number 6,
November-December 2004
Editor-in-Chief's Message
Micro Economics
Micro's Top Picks from Microarchitecture Conferences
- David H. Albonesi:
Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences.
8-9
Electronic Edition (link) BibTeX
- Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner:
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.
10-20
Electronic Edition (link) BibTeX
- Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth.
22-29
Electronic Edition (link) BibTeX
- Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt:
Reducing the Soft-Error Rate of a High-Performance Microprocessor.
30-37
Electronic Edition (link) BibTeX
- Xiaodong Li, Zhenmin Li, Pin Zhou, Yuanyuan Zhou, Sarita V. Adve, Sanjeev Kumar:
Performance-Directed Energy Management for Storage Systems.
38-49
Electronic Edition (link) BibTeX
- Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas:
iWatcher: Simple, General Architectural Support for Software Debugging.
50-56
Electronic Edition (link) BibTeX
- Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn:
Interaction Cost: For When Event Counts Just Don't Add Up.
57-61
Electronic Edition (link) BibTeX
- Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton:
Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance.
62-73
Electronic Edition (link) BibTeX
- Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen:
Helper Threads via Virtual Multithreading.
74-82
Electronic Edition (link) BibTeX
- Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic:
The Vector-Thread Architecture.
84-90
Electronic Edition (link) BibTeX
- Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael K. Chen, Christos Kozyrakis, Kunle Olukotun:
Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software.
92-103
Electronic Edition (link) BibTeX
- Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi:
Speculative Incoherent Cache Protocols.
104-109
Electronic Edition (link) BibTeX
- Harold W. Cain, Mikko H. Lipasti:
Memory Ordering: A Value-Based Approach.
110-117
Electronic Edition (link) BibTeX
- Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High-ILP Processors.
118-127
Electronic Edition (link) BibTeX
Departments
Copyright © Sun May 17 00:13:21 2009
by Michael Ley (ley@uni-trier.de)
