Joao Geada

2008
3	EE	S. Raja, F. Varadi, Murat R. Becer, Joao Geada: Transistor level gate modeling for accurate and fast timing, noise, and power analysis. DAC 2008: 456-461
2007
2	EE	Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
2001
1	EE	Surrendra Dudani, Joao Geada, Grzegorz Jakacki, Daniel Vainer: Dynamic Assertions Using TXP. Electr. Notes Theor. Comput. Sci. 55(2): (2001)

Coauthor Index

1	Murat R. Becer	[2] [3]
2	David Blaauw (David T. Blaauw)	[2]
3	Kaviraj Chopra	[2]
4	Surrendra Dudani	[1]
5	Ravikishore Gandikota	[2]
6	Grzegorz Jakacki	[1]
7	S. Raja	[3]
8	Dennis Sylvester	[2]
9	Daniel Vainer	[1]
10	F. Varadi	[3]

Colors in the list of coauthors