ISQED 2001:
San Jose,
California,
USA
2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA.
IEEE Computer Society 2001, ISBN 0-7695-1025-6 BibTeX
@proceedings{DBLP:conf/isqed/2001,
title = {2nd International Symposium on Quality of Electronic Design (ISQED
2001), 26-28 March 2001, San Jose, CA, USA},
booktitle = {ISQED},
publisher = {IEEE Computer Society},
year = {2001},
isbn = {0-7695-1025-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Tutorial
- Yervant Zorian:
System-on-Chip: Embedded Test Strategies.
7
Electronic Edition (link) BibTeX
- Kaushik Roy, Ali Keshavarzi:
Design and Test of Low Voltage CMOS Circuits.
7
Electronic Edition (link) BibTeX
- Mo Tamjidi, Bejoy G. Oomman:
Redundancy Requirements for Embedded Memories.
8
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats:
Design Metrics to Achieve Design Quality.
9
Electronic Edition (link) BibTeX
- Phil Dworsky, Warren Savage:
Fundamental Methods to Enable SoC Design and Reuse.
9
Electronic Edition (link) BibTeX
- Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design.
10
Electronic Edition (link) BibTeX
- Noel R. Strader, Gérard Memmi, Carl Pixley:
Application of Formal Verification to Design Creation and Implementation.
11
Electronic Edition (link) BibTeX
- Magdy S. Abadir, Li-C. Wang:
Verification and Validation of Complex Digital Systems: An Industrial Perspective.
11-12
Electronic Edition (link) BibTeX
- Daniel Foty, David Binkley:
Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality.
13
Electronic Edition (link) BibTeX
- Narain Arora, N. S. Nagaraj:
Interconnect Modeling for Timing, Signal Integrity and Reliability.
13
Electronic Edition (link) BibTeX
- David Blaauw, Rajendran Panda:
On-Chip Inductance Extraction and Modelin.
14
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Evening Panel Discussion
Plenary Session
Impact of Verification on Complex SOC Quality
- Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman:
Stopping Criteria Comparison: Towards High Quality Behavioral Verification.
31-37
Electronic Edition (link) BibTeX
- Umberto Rossi, Andrea Fedeli, Marco Boschini, Franco Toto:
Concrete Impact of Formal Verification on Quality in IP Design and Implementation.
38-43
Electronic Edition (link) BibTeX
- Zan Yang, Byeong Min, Gwan Choi:
Simulation Using Code-Perturbation: Black- and White-Box Approach.
44-49
Electronic Edition (link) BibTeX
- F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi:
A "Design for Verification" Methodology.
50-55
Electronic Edition (link) BibTeX
- Mohammed El Shobaki, Lennart Lindh:
A Hardware and Software Monitor for High-Level System-on-Chip Verification.
56-
Electronic Edition (link) BibTeX
Quality of EDA Tools and Design Methodologies
Design,
Fabrication and Reliability Challenges for Emerging Technologies
Capacitive Crosstalk Analysis
- Ninglong Lu, Ibrahim N. Hajj:
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model.
133-138
Electronic Edition (link) BibTeX
- Pirouz Bazargan-Sabet, Fabrice Ilponse:
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes.
139-144
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani:
Noise Model for Multiple Segmented Coupled RC Interconnects.
145-150
Electronic Edition (link) BibTeX
- Qingjian Yu, Ernest S. Kuh:
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees.
151-157
Electronic Edition (link) BibTeX
- Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
158-
Electronic Edition (link) BibTeX
Interconnect Modeling and Analysis
Power-Aware Design
- Wei-Chung Cheng, Massoud Pedram:
Memory Bus Encoding for Low Power: A Tutorial.
199-204
Electronic Edition (link) BibTeX
- Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
205-210
Electronic Edition (link) BibTeX
- Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa:
Instruction Prediction for Step Power Reduction.
211-216
Electronic Edition (link) BibTeX
- Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations.
217-222
Electronic Edition (link) BibTeX
- Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez:
A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits.
223-
Electronic Edition (link) BibTeX
Evening Panel Discussion
Plenary Session II
Ph.D. Student Forum
Poster Session
- Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang:
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.
267-272
Electronic Edition (link) BibTeX
- Alexander Zemliak:
One Approach to Analog System Design Problem Formulation.
273-278
Electronic Edition (link) BibTeX
- Mark Birnbaum, Charlene C. Johnson:
VSIA Quality Metrics for IP and SoC.
279-283
Electronic Edition (link) BibTeX
- Wei Li, Qiang Li, J. S. Yuan, Joshua McConkey, Yuan Chen, Sundar Chetlur, Jonathan Zhou, A. S. Oates:
Hot-carrier-Induced Circuit Degradation for 0.18 ?m CMOS Technology.
284-289
Electronic Edition (link) BibTeX
- Tom Egan, Samiha Mourad:
Verification of Embedded Phase-Locked Loops.
290-295
Electronic Edition (link) BibTeX
- Alexander Korshak, Jyh-Chwen Lee:
An Effective Current Source Cell Model for VDSM Delay Calculation.
296-300
Electronic Edition (link) BibTeX
- Mehdi M. Mechaik:
An Evaluation of Single-Ended and Differential Impedance in PCBs.
301-306
Electronic Edition (link) BibTeX
- Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng:
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.
307-312
Electronic Edition (link) BibTeX
- Ning Zhu, Han Young Koh:
Power Grid Modeling Technique for Hierarchical Power Network Analysis.
313-318
Electronic Edition (link) BibTeX
- Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi:
Energy Efficient Signaling in Deep Submicron CMOS Technology.
319-324
Electronic Edition (link) BibTeX
- Rong Lin:
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design.
325-330
Electronic Edition (link) BibTeX
- Mihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca:
Complex Reliability Evaluation of Voters for Fault Tolerant Designs.
331-336
Electronic Edition (link) BibTeX
- Josef Schmid, Timo Schüring, Christoph Smalla:
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.
337-342
Electronic Edition (link) BibTeX
- Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.
343-349
Electronic Edition (link) BibTeX
- Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes.
350-
Electronic Edition (link) BibTeX
Defect Analysis and Test Generation
Design of Programmable and Platform-Based IP
- Rafael Peset Llopis, Marcel Oosterhuis, Ramanathan Sethuraman, Paul E. R. Lippens, Albert van der Werf, Steffen Maul, Jim Lin:
HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec.
393-398
Electronic Edition (link) BibTeX
- Martin Speitel, Michael Schlicht, Martin Leyh:
Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis.
399-404
Electronic Edition (link) BibTeX
- Chih-Yuan Chen, Shing-Wu Tung:
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality.
405-408
Electronic Edition (link) BibTeX
- Artur Chojnacki, Lech Józwiak:
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.
409-414
Electronic Edition (link) BibTeX
- Kazimierz Wiatr, Ernest Jamro:
Implementation of Multipliers in FPGA Structures.
415-
Electronic Edition (link) BibTeX
Embedded Panel Discussion
Design for Manufacturability
- Ron Ross, Keith McCasland:
Early Detection of Design Sensitivities that Cause Yield Loss for New Products.
427-430
Electronic Edition (link) BibTeX
- Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu:
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.
431-436
Electronic Edition (link) BibTeX
- Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long:
Timing Yield Estimation from Static Timing Analysis.
437-442
Electronic Edition (link) BibTeX
- Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong:
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model.
443-
Electronic Edition (link) BibTeX
Embedded Memories
Device Modeling and Design Quality
- Amit Mehrotra:
Noise in Radio Frequency Circuits: Analysis and Design Implications.
469-476
Electronic Edition (link) BibTeX
- Peter Bendix:
Spice Model Quality: Process Development Viewpoint.
477-481
Electronic Edition (link) BibTeX
- Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.
482-487
Electronic Edition (link) BibTeX
- Stefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Modeling of Substrate Noise Injected by Digital Libraries.
488-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:17 2009
by Michael Ley (ley@uni-trier.de)