12. PATMOS 2002:
Seville,
Spain
Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido (Eds.):
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002.
Lecture Notes in Computer Science 2451 Springer 2002, ISBN 3-540-44143-3 BibTeX
@proceedings{DBLP:conf/patmos/2002,
editor = {Bertrand Hochet and
Antonio J. Acosta and
Manuel J. Bellido},
title = {Integrated Circuit Design. Power and Timing Modeling, Optimization
and Simulation, 12th International Workshop, PATMOS 2002, Seville,
Spain, September 11-13, 2002},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {2451},
year = {2002},
isbn = {3-540-44143-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Opening
Arithmetics
Low-Level Modeling and Characterization
- Juan Antonio Carballo, Sani R. Nassif:
Impact of Technology in Power-Grid-Induced Noise.
45-54
Electronic Edition (link) BibTeX
- Armin Windschiegl, Paul Zuber, Walter Stechele:
Exploiting Metal Layer Characteristics for Low-Power Routing.
55-64
Electronic Edition (link) BibTeX
- Fabrice Picot, Philippe Coll, Daniel Auvergne:
Crosstalk Measurement Technique for CMOS ICs.
65-70
Electronic Edition (link) BibTeX
- Spiridon Nikolaidis, Nikolaos Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, Labros Bisdounis:
Instrumentation Set-up for Instruction Level Power Modeling.
71-80
Electronic Edition (link) BibTeX
Asynchronous and Adiabatic Techniques
CAD Tools and Algorithms
- Vojin G. Oklobdzija:
Clocking and Clocked Storage Elements in Multi-GHz Environment.
128-145
Electronic Edition (link) BibTeX
- Torsten Mahnke, Walter Stechele, Wolfgang Hoeld:
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment.
146-155
Electronic Edition (link) BibTeX
- A. Landrault, L. Pellier, A. Richard, C. Jay, Michel Robert, Daniel Auvergne:
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.
156-166
Electronic Edition (link) BibTeX
- Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw:
Robust SAT-Based Search Algorithm for Leakage Power Reduction.
167-177
Electronic Edition (link) BibTeX
Timing
- Kyu-won Choi, Abhijit Chatterjee:
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI.
178-187
Electronic Edition (link) BibTeX
- Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz:
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems.
188-197
Electronic Edition (link) BibTeX
- Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni:
Clock Distribution Network Optimization under Self-Heating and Timing Constraints.
198-208
Electronic Edition (link) BibTeX
- Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta:
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.
209-218
Electronic Edition (link) BibTeX
Gate-Level Modeling
Memory Optimization
- Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal:
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.
258-267
Electronic Edition (link) BibTeX
- Xuemei Zhao, Yizheng Ye:
Design and Realization of a Low Power Register File Using Energy Model.
268-277
Electronic Edition (link) BibTeX
- Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga:
Register File Energy Reduction by Operand Data Reuse.
278-288
Electronic Edition (link) BibTeX
- Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose:
Energy-Efficient Design of the Reorder Buffer.
289-299
Electronic Edition (link) BibTeX
High-Level Modeling and Design
Communications Modeling and Activity Reduction
- Claudia Kretzschmar, Robert Siegmund, Dietmar Müller:
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission.
342-352
Electronic Edition (link) BibTeX
- C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia:
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.
353-362
Electronic Edition (link) BibTeX
- Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
Low-Power FSMs in FPGA: Encoding Alternatives.
363-370
Electronic Edition (link) BibTeX
- Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit, Bernabé Linares-Barranco:
Synthetic Generation of Events for Address-Event-Representation Communications.
371-379
Electronic Edition (link) BibTeX
Posters
- Toshinori Sato, Itsujiro Arita:
Reducing Energy Consumption via Low-Cost Value Prediction.
380-389
Electronic Edition (link) BibTeX
- Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin:
Dynamic Voltage Scheduling for Real Time Asynchronous Systems.
390-399
Electronic Edition (link) BibTeX
- Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero:
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.
400-408
Electronic Edition (link) BibTeX
- Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis:
Power Efficient Vector Quantization Design Using Pixel Truncation.
409-418
Electronic Edition (link) BibTeX
- Artur Wróblewski, Florian Auernhammer, Josef A. Nossek:
Minimizing Spurious Switching Activities in CMOS Circuits.
419-428
Electronic Edition (link) BibTeX
- Massimo Alioto, Gaetano Palumbo:
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.
429-437
Electronic Edition (link) BibTeX
- Gregorio Cappuccino, Giuseppe Cocorullo:
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
438-447
Electronic Edition (link) BibTeX
- Pilar Parra, Antonio J. Acosta, Manuel Valencia:
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.
448-457
Electronic Edition (link) BibTeX
- Achim Freimann:
Probabilistic Power Estimation for Digital Signal Processing Architectures.
458-467
Electronic Edition (link) BibTeX
- Rosario Mita, Gaetano Palumbo:
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.
468-476
Electronic Edition (link) BibTeX
- Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero:
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).
477-486
Electronic Edition (link) BibTeX
- Razvan Ionita, Andrei Vladimirescu, Paul G. A. Jespers:
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.
487-494
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:32:37 2009
by Michael Ley (ley@uni-trier.de)
