32. ISCA 2005:
Madison,
Wisconsin,
USA
32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA.
IEEE Computer Society 2005 BibTeX
Session 1:
Security
- Ruby B. Lee, Peter C. S. Kwan, John Patrick McGregor, Jeffrey S. Dwoskin, Zhenghong Wang:
Architecture for Protecting Critical Secrets in Microprocessors.
2-13
Electronic Edition (link) BibTeX
- Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva:
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation.
14-24
Electronic Edition (link) BibTeX
- G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas:
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.
25-36
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Session 2a:
Interacting with Disks and Networks
Session 2b:
Memory Compression and Renamer Optimizations
Session 3a:
Specialized Processors
Session 3b:
Detecting Faults
Session 4a:
Quantum Computing and Very Low Power
- Steven Balensiefer, Lucas Kreger-Stickles, Mark Oskin:
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures.
186-196
Electronic Edition (link) BibTeX
- Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw:
Energy Optimization of Subthreshold-Voltage Sensor Network Processors.
197-207
Electronic Edition (link) BibTeX
- Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks:
An Ultra Low Power System Architecture for Sensor Network Applications.
208-219
Electronic Edition (link) BibTeX
Session 4b:
Coherence
Session 5a:
Applying Compilers and Debugging Support
- Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley:
Improving Program Efficiency by Packing Instructions into Registers.
260-271
Electronic Edition (link) BibTeX
- Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner:
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors.
272-283
Electronic Edition (link) BibTeX
- Satish Narayanasamy, Gilles Pokam, Brad Calder:
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging.
284-295
Electronic Edition (link) BibTeX
Session 5b:
Power
Session 6a:
Chip Multiprocessor Memory Hierarchies
Session 6b:
Runahead and Branch Prediction
Session 7a:
Interconnection Networks
- Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen:
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.
408-419
Electronic Edition (link) BibTeX
- John Kim, William J. Dally, Brian Towles, Amit K. Gupta:
Microarchitecture of a High-Radix Router.
420-431
Electronic Edition (link) BibTeX
- Daeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique, Mithuna Thottethodi:
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks.
432-443
Electronic Edition (link) BibTeX
Session 7b:
Load and Store Queues
Session 8a:
Multiprocessor Issues
Session 8b:
Reliability and a Cache Organization
- Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Exploiting Structural Duplication for Lifetime Reliability Enhancement.
520-531
Electronic Edition (link) BibTeX
- Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan:
Computing Architectural Vulnerability Factors for Address-Based Structures.
532-543
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- Moinuddin K. Qureshi, David Thompson, Yale N. Patt:
The V-Way Cache: Demand Based Associativity via Global Replacement.
544-555
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:24:58 2009
by Michael Ley (ley@uni-trier.de)
