2007 |
12 | EE | Rajiv V. Joshi,
Keunwoo Kim,
Richard Q. Williams,
Edward J. Nowak,
Ching-Te Chuang:
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.
VLSI Design 2007: 665-672 |
2006 |
11 | EE | Wilfried Haensch,
Edward J. Nowak,
Robert H. Dennard,
Paul M. Solomon,
Andres Bryant,
Omer H. Dokumaci,
Arvind Kumar,
Xinlin Wang,
Jeffrey B. Johnson,
Massimo V. Fischetti:
Silicon CMOS devices beyond scaling.
IBM Journal of Research and Development 50(4-5): 339-362 (2006) |
10 | EE | Kerry Bernstein,
David J. Frank,
Anne E. Gattiker,
Wilfried Haensch,
Brian L. Ji,
Sani R. Nassif,
Edward J. Nowak,
Dale J. Pearson,
Norman J. Rohrer:
High-performance CMOS variability in the 65-nm regime and beyond.
IBM Journal of Research and Development 50(4-5): 433-450 (2006) |
9 | EE | Scott Hanson,
Bo Zhai,
Kerry Bernstein,
David Blaauw,
Andres Bryant,
Leland Chang,
Koushik K. Das,
Wilfried Haensch,
Edward J. Nowak,
Dennis Sylvester:
Ultralow-voltage, minimum-energy CMOS.
IBM Journal of Research and Development 50(4-5): 469-490 (2006) |
2003 |
8 | EE | Ernest Y. Wu,
Jordi Suñé,
Wing L. Lai,
Alex Vayshenker,
Edward J. Nowak,
David L. Harmon:
Critical reliability challenges in scaling SiO2-based dielectric to its limit.
Microelectronics Reliability 43(8): 1175-1184 (2003) |
2002 |
7 | EE | Edward J. Nowak:
Maintaining the benefits of CMOS scaling when scaling bogs down.
IBM Journal of Research and Development 46(2-3): 169-186 (2002) |
6 | EE | Ernest Y. Wu,
Edward J. Nowak,
Alex Vayshenker,
Wing L. Lai,
David L. Harmon:
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics.
IBM Journal of Research and Development 46(2-3): 287-298 (2002) |
1996 |
5 | EE | Kerry Bernstein,
John E. Bertsch,
William F. Clark,
John J. Ellis-Monaghan,
Larry G. Heller,
Edward J. Nowak:
Practical performance/power alternatives within an existing CMOS technology generation.
ISLPED 1996: 365-370 |
1995 |
4 | | Donald G. Chesebro,
James W. Adkisson,
Lyman R. Clark,
Steven N. Eslinger,
Margaret A. Faucher,
Steven J. Holmes,
Raymond P. Mallette,
Edward J. Nowak,
Edward W. Sengle,
Steven H. Voldman,
Thomas W. Weeks:
Overview of gate linewidth control in the manufacture of CMOS logic chips.
IBM Journal of Research and Development 39(1-2): 189-200 (1995) |
3 | | Charles W. Koburger III,
William F. Clark,
James W. Adkisson,
Eric Adler,
Paul E. Bakeman,
Albert S. Bergendahl,
Alan B. Botula,
W. Chang,
Bijan Davari,
John H. Givens,
Howard H. Hansen,
Steven J. Holmes,
David V. Horak,
Chung Hon Lam,
Jerome B. Lasky,
Stephen E. Luce,
Randy W. Mann,
Glen L. Miles,
James S. Nakos,
Edward J. Nowak,
Ghavam Shahidi,
Yuan Taur,
Francis R. White,
Matthew R. Wordeman:
A half-micron CMOS logic generation.
IBM Journal of Research and Development 39(1-2): 215-228 (1995) |
2 | | Yuan Taur,
Yuh-Jier Mii,
David J. Frank,
H.-S. Philip Wong,
Douglas A. Buchanan,
Shalom J. Wind,
Stephen A. Rishton,
Watson A. Sai-Halasz,
Edward J. Nowak:
CMOS scaling into the 21st century: 0.1 µm and beyond.
IBM Journal of Research and Development 39(1-2): 245-260 (1995) |
1 | | Kerry Bernstein,
John E. Bertsch,
Lawrence G. Heller,
Edward J. Nowak,
Francis R. White:
Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor.
IBM Journal of Research and Development 39(1-2): 33-42 (1995) |