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16. PATMOS 2006: Montpellier, France

Johan Vounckx, Nadine Azémard, Philippe Maurine (Eds.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. Lecture Notes in Computer Science 4148 Springer 2006, ISBN 3-540-39094-4 BibTeX

High-Level Design

Power Estimation / Modeling

Memory and Register Files

Low-Power Digital Circuits

Busses and Interconnects

Low Power Techniques

Applications and SoC Design


Digital Circuits

Reconfigurable and Programmable Devices

Poster 1

Poster 2

Poster 3


Industrial Session

Copyright © Sat May 16 23:32:38 2009 by Michael Ley (ley@uni-trier.de)