PACT 2007:
Brasov,
Romania
16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007.
IEEE Computer Society 2007 BibTeX
Hardware Track (Session 1):
Systems
- Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally:
Architectural Support for the Stream Execution Model on General-Purpose Processors.
3-12
Electronic Edition (link) BibTeX
- Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero:
A Flexible Heterogeneous Multi-Core Architecture.
13-24
Electronic Edition (link) BibTeX
- Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith:
Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler.
25-38
Electronic Edition (link) BibTeX
Software Track (Session 2):
Pipelining
Hardware Track (Session 3):
Verification & Security
Software Track (Session 4):
Optimizations
Hardware Track (Session 5):
Saving Energy
Software Track (Session 6):
Algorithms
Hardware Track (Session 7):
Processors
Software Track (Session 8):
Compilers
Hardware Track (Session 9):
Modeling & Measurement
- Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero:
FAME: FAirly MEasuring Multithreaded Architectures.
305-316
Electronic Edition (link) BibTeX
- John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu:
CIGAR: Application Partitioning for a CPU/Coprocessor Architecture.
317-326
Electronic Edition (link) BibTeX
- Salman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra:
Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems.
327-338
Electronic Edition (link) BibTeX
- Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Moses, Srihari Makineni, Donald Newell:
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms.
339-352
Electronic Edition (link) BibTeX
Software Track (Session 10):
Transactional Memory & Locks
- Richard L. Halpert, Christopher J. F. Pickett, Clark Verbrugge:
Component-Based Lock Allocation.
353-364
Electronic Edition (link) BibTeX
- Marek Olszewski, Jeremy Cutler, J. Gregory Steffan:
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory.
365-375
Electronic Edition (link) BibTeX
- Woongki Baek, Chi Cao Minh, Martin Trautmann, Christos Kozyrakis, Kunle Olukotun:
The OpenTM Transactional Application Programming Interface.
376-387
Electronic Edition (link) BibTeX
- Ian Watson, Chris C. Kirkham, Mikel Luján:
A Study of a Transactional Parallel Routing Algorithm.
388-398
Electronic Edition (link) BibTeX
Poster Abstracts
- Sayaka Akioka, Feihui Li, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin:
Ring Prediction for Non-Uniform Cache Architectures.
401
Electronic Edition (link) BibTeX
- Yosi Ben-Asher, Moshe Yuda:
Source Level Merging of Independent Programs.
402
Electronic Edition (link) BibTeX
- Florina M. Ciorba, Ioannis Riakiotakis, George K. Papakonstantinou, Theodore Andronikos, Anthony T. Chronopoulos:
Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systems.
403
Electronic Edition (link) BibTeX
- Lionel Damez, Jean-Pierre Dérutin:
Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processors.
404
Electronic Edition (link) BibTeX
- Abhishek Das, William J. Dally:
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy.
405
Electronic Edition (link) BibTeX
- Stijn Eyerman, Lieven Eeckhout, James E. Smith:
Studying Compiler-Microarchitecture Interactions through Interval Analysis.
406
Electronic Edition (link) BibTeX
- John Giacomoni, Tipp Moseley, Manish Vachharajani:
FastForward for Efficient Pipeline Parallelism.
407
Electronic Edition (link) BibTeX
- Sven Groot, Harmen L. A. van der Spek, Erwin M. Bakker, Harry A. G. Wijshoff:
The Automatic Transformation of Linked List Data Structures.
408
Electronic Edition (link) BibTeX
- Marco Höbbel, Thomas Rauber, Carsten Scholtes:
Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization Interface.
409
Electronic Edition (link) BibTeX
- Changjun Hu, Jilin Zhang, Jue Wang, Jianjiang Li, Liang Ding:
A New Parallel Gauss-Seidel Method by Iteration Space Alternate Tiling.
410
Electronic Edition (link) BibTeX
- Costin Iancu, Wei Chen, Katherine A. Yelick:
Performance Portable Optimizations for Loops Containing Communication Operations.
411
Electronic Edition (link) BibTeX
- Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John:
Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks.
412
Electronic Edition (link) BibTeX
- Simo Juvaste:
Studying Asynchronous Shared Memory Computations.
413
Electronic Edition (link) BibTeX
- Kirk Kelsey, Chengliang Zhang, Chen Ding:
Fast Track: Supporting Unsafe Optimizations with Software Speculation.
414
Electronic Edition (link) BibTeX
- Minhaj Ahmad Khan, Henri-Pierre Charles, Denis Barthou:
Hybrid Specialization: A Trade-off Between Static and Dynamic Specialization.
415
Electronic Edition (link) BibTeX
- Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares:
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.
416
Electronic Edition (link) BibTeX
- Georgiana Macariu, Marc Frîncu, Alexandru Cârstea, Dana Petcu, Andrei Eckstein:
Redesigning Parallel Symbolic Computations Packages.
417
Electronic Edition (link) BibTeX
- Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning.
418
Electronic Edition (link) BibTeX
- Cosmin E. Oancea, Alan Mycroft:
A Lightweight Model for Software Thread-Level Speculation (TLS).
419
Electronic Edition (link) BibTeX
- Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso:
HelperCore_DB: Exploiting Multicore Technology for Databases.
420
Electronic Edition (link) BibTeX
- Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, N. Voros:
Data Structure Exploration of Dynamic Applications.
421
Electronic Edition (link) BibTeX
- Kaushik Rajan, R. Govindarajan, Bharadwaj Amrutur:
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses.
422
Electronic Edition (link) BibTeX
- Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Runahead Threads: Reducing Resource Contention in SMT Processors.
423
Electronic Edition (link) BibTeX
- Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev:
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.
424
Electronic Edition (link) BibTeX
- Harald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jimenez:
Drug Design on the Cell BroadBand Engine.
425
Electronic Edition (link) BibTeX
- Xipeng Shen, Feng Mao:
Bridging Inputs and Program Dynamic Behavior.
426
Electronic Edition (link) BibTeX
- Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor.
427
Electronic Edition (link) BibTeX
- Jaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande:
RSTM : A Relaxed Consistency Software Transactional Memory for Multicores.
428
Electronic Edition (link) BibTeX
- Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors.
429
Electronic Edition (link) BibTeX
- Rajesh Vivekanandham, R. Govindarajan:
A Scalable Low Power Store Queue for Large InstructionWindow Processors.
430
Electronic Edition (link) BibTeX
- Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Adapting to Intermittent Faults in Future Multicore Systems.
431
Electronic Edition (link) BibTeX
- Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke:
A Phase-Adaptive Approach to Increasing Cache Performance.
432
Electronic Edition (link) BibTeX
- Jing Yu, María Jesús Garzarán:
Compiler Optimizations for Fault Tolerance Software Checking.
433
Electronic Edition (link) BibTeX
- Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu:
Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors.
434
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:22:28 2009
by Michael Ley (ley@uni-trier.de)
