| |
| 2002 | ||
|---|---|---|
| 1 | EE | Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002) |
| 1 | David Blaauw (David T. Blaauw) | [1] |
| 2 | Kaushik Gala | [1] |
| 3 | A. Joshi | [1] |
| 4 | Vladimir Zolotov | [1] |