ISLPD 1995:
Dana Point,
California,
USA
Massoud Pedram, Robert W. Brodersen, Kurt Keutzer (Eds.):
Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995.
ACM 1995, ISBN 0-89791-744-8 BibTeX
@proceedings{DBLP:conf/islped/1995,
editor = {Massoud Pedram and
Robert W. Brodersen and
Kurt Keutzer},
title = {Proceedings of the 1995 International Symposium on Low Power
Design 1995, Dana Point, California, USA, April 23-26, 1995},
booktitle = {ISLPD},
publisher = {ACM},
year = {1995},
isbn = {0-89791-744-8},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
- Walter Davis:
The CAD challenges of designing low power, high performance VLSI system.
1
Electronic Edition (ACM DL) BibTeX
- Kimiyoshi Usami, Mark Horowitz:
Clustered voltage scaling technique for low-power design.
3-8
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- Salil Raje, Majid Sarrafzadeh:
Variable voltage scheduling.
9-14
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- Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Unifying carry-sum and signed-digital number representations for low power.
15-20
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- Luca Benini, Giovanni De Micheli:
Transformation and synthesis of FSMs for low-power gated-clock implementation.
21-26
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- Christos A. Papachristou, Mark Spining, Mehrdad Nourani:
A multiple clocking scheme for low power RTL design.
27-32
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- José Monteiro, Srinivas Devadas:
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs.
33-38
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- Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar:
Estimation of energy consumption in speed-independent control circuits.
39-44
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- Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multi-level processor cache architectures.
45-49
Electronic Edition (ACM DL) BibTeX
- Sven Wuytack, Francky Catthoor, Hugo De Man:
Transforming set data types to power optimal data structures.
51-56
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- Ramesh Panwar, David A. Rennels:
Reducing the frequency of tag compares for low power I-cache design.
57-62
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- Ching-Long Su, Alvin M. Despain:
Cache design trade-offs for power and performance optimization: a case study.
63-68
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- Aurobindo Dasgupta, Ramesh Karri:
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis.
69-74
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- Anthony Correale Jr.:
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers.
75-80
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- Diana Marculescu, Radu Marculescu, Massoud Pedram:
Information theoretic measures of energy consumption at register transfer level.
81-86
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- Farid N. Najm:
Towards a high-level power estimation capability.
87-92
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- Paul E. Landman, Jan M. Rabaey:
Activity-sensitive architectural power analysis for the control path.
93-98
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- Enric Musoll, Jordi Cortadella:
High-level synthesis techniques for reducing the activity of functional units.
99-104
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- Charlie X. Huang, Bill Zhang, An-Chang Deng, Burkhard Swirski:
The design and implementation of PowerMill.
105-110
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- Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi:
CMOS dynamic power estimation based on collapsible current source transistor modeling.
111-116
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- Christian Piguet, Jean-Marc Masgonty, V. von Kaenel, T. Schneider:
Logic design for low-voltage/low-power CMOS circuits.
117-122
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- Michele Favalli, Luca Benini:
Analysis of glitch power dissipation in CMOS ICs.
123-128
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- S. Turgis, Nadine Azémard, Daniel Auvergne:
Explicit evaluation of short circuit power dissipation for CMOS logic structures.
129-134
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- Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh:
Techniques for fast circuit simulation applied to power estimation of CMOS circuits.
135-138
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- Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
High-throughput and low-power DSP using clocked-CMOS circuitry.
139-144
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- William A. Chren Jr.:
Low delay-power product CMOS design using one-hot residue coding.
145-150
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- Rafael Fried, Reuven Holzer:
Low power and EMI, high frequency, crystal oscillator.
151-154
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- M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto:
Power and area optimization by reorganizing CMOS complex gate circuits.
155-160
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- Alexey Glebov, David Blaauw, Larry G. Jones:
Transistor reordering for low power CMOS gates using an SP-BDD representation.
161-166
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- Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint.
167-172
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- Vamshi Veeramachaneni, Akhilesh Tyagi, Suresh Rajgopal:
Re-encoding for low power state assignment of FSMs.
173-178
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- Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization of power dissipation and skew sensitivity in clock buffer synthesis.
179-184
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- Kei-Yong Khoo, Alan N. Willson Jr.:
Charge recovery on a databus.
185-189
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- Alan Kramer, John S. Denker, B. Flower, J. Moroney:
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits.
191-196
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- David J. Frank, Paul M. Solomon:
Electroid-oriented adiabatic switching circuits.
197-202
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- Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, M. Sabatini, P. Zabberoni:
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors.
203-208
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- Phillip E. Allen, Benjamin J. Blalock, Gabriel A. Rincon:
Low voltage analog circuits using standard CMOS technology.
209-214
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- Anthony M. Hill, Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation.
215-220
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- Vivek Tiwari, Sharad Malik, Pranav Ashar:
Guarded evaluation: pushing power management to logic synthesis/design.
221-226
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- Christopher K. Lennard, A. Richard Newton:
An estimation technique to guide low power resynthesis algorithms.
227-232
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Copyright © Sat May 16 23:25:40 2009
by Michael Ley (ley@uni-trier.de)