41. MICRO 2008:
Lake Como,
Italy
41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy.
IEEE Computer Society 2008 BibTeX
Keynote 1
Instruction-Level Parallelism
- David E. Shaw:
Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins.
Electronic Edition (link) BibTeX
- Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos:
Temporal instruction fetch streaming.
1-10
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- Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero:
A distributed processor state management architecture for large-window processors.
11-22
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- Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley:
Strategies for mapping dataflow blocks to distributed hardware.
23-34
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Cache Coherence and Cache Modeling
Cache Architectures for Security and Availability
- Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan:
Implementing high availability memory with a duplication cache.
71-82
Electronic Edition (link) BibTeX
- Zhenghong Wang, Ruby B. Lee:
A novel cache architecture with enhanced performance and security.
83-93
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- Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood:
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.
94-105
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Reliability,
Availability,
Security
- Vikas R. Vasisht, Hsien-Hsin S. Lee:
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits.
106-116
Electronic Edition (link) BibTeX
- Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie:
Testudo: Heavyweight security analysis via statistical sampling.
117-128
Electronic Edition (link) BibTeX
- Abhishek Tiwari, Josep Torrellas:
Facelift: Hiding and slowing down aging in multicores.
129-140
Electronic Edition (link) BibTeX
- Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke:
The StageNet fabric for constructing resilient multicore systems.
141-151
Electronic Edition (link) BibTeX
Embedded and Special Purpose Architectures
- Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner:
From SODA to scotch: The evolution of a wireless baseband processor.
152-163
Electronic Edition (link) BibTeX
- Aqeel Mahesri, Daniel Johnson, Neal Crago, Sanjay J. Patel:
Tradeoffs in designing accelerator architectures for visual computing.
164-175
Electronic Edition (link) BibTeX
- Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary Vernon, William R. Mark:
Toward a multicore architecture for real-time ray-tracing.
176-187
Electronic Edition (link) BibTeX
- Alex Shye, Yan Pan, Ben Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick:
Power to the people: Leveraging human physiological traits to control microprocessor frequency.
188-199
Electronic Edition (link) BibTeX
Memory and Cache Architectures
- Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt:
Prefetch-Aware DRAM Controllers.
200-209
Electronic Edition (link) BibTeX
- Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu:
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.
210-221
Electronic Edition (link) BibTeX
- Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger:
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.
222-233
Electronic Edition (link) BibTeX
Transactions and Runtime Systems
Modeling,
Simulation and Verification
- Benjamin C. Lee, Jamison Collins, Hong Wang, David Brooks:
CPR: Composable performance regression for scalable multiprocessor models.
270-281
Electronic Edition (link) BibTeX
- Kypros Constantinides, Onur Mutlu, Todd M. Austin:
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation.
282-293
Electronic Edition (link) BibTeX
- Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz:
Verification of chip multiprocessor memory systems using a relaxed scoreboard.
294-305
Electronic Edition (link) BibTeX
Multicore and Multithreading
Interconnects
- Amit Kumar, Li-Shiuan Peh, Niraj K. Jha:
Token flow control.
342-353
Electronic Edition (link) BibTeX
- Yuho Jin, Ki Hwan Yum, Eun Jung Kim:
Adaptive data compression for high-performance low-power on-chip networks.
354-363
Electronic Edition (link) BibTeX
- Samuel Rodrigo, Jose Flich, José Duato, Mark Hummel:
Efficient unicast and multicast support for CMPs.
364-375
Electronic Edition (link) BibTeX
- M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam:
Power reduction of CMP communication networks via RF-interconnects.
376-387
Electronic Edition (link) BibTeX
Process Variation
- Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Evaluating the effects of cache redundancy on profit.
388-398
Electronic Edition (link) BibTeX
- Xin Fu, Tao Li, José A. B. Fortes:
NBTI tolerant microarchitecture design in the presence of process variation.
399-410
Electronic Edition (link) BibTeX
- Eric Chun, Zeshan Chishti, T. N. Vijaykumar:
Shapeshifter: Dynamically changing pipeline width and speed to address process variations.
411-422
Electronic Edition (link) BibTeX
- Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas:
EVAL: Utilizing processors with variation-induced timing errors.
423-434
Electronic Edition (link) BibTeX
Circuits and Microarchitectures
Copyright © Sat May 16 23:29:55 2009
by Michael Ley (ley@uni-trier.de)
