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15. FPL 2005: Tampere, Finland

Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong (Eds.): Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. IEEE 2005, ISBN 0-7803-9362-7 BibTeX

Embedded Soft Processors

Logic Synthesis

Networking Applications 1

Chip Communication Architectures

CAD for Coarse-Grained Logic

SAT Solvers and Neural Networks

Chip Architectures


Video Processing Applications 1

Run-Time Reconfigurable Architectures and Applications

Routing Characterization

Multidimensional Processing

Network on Chip Architectures

Tools and Methods for Run-Time Reconfiguration

Implementation Techniques

Defect Tolerance

Compilation Methods 1

Cryptography Applications

Asynchronous Architectures

Compilation Methods 2

Bio-Inspired Computing

System Architecture Exploration and Evaluation

Communication Synthesis and High Level Design

MPEG Applications

Fault Tolerant Architectures and Systems


Security Attacks and Detection

Video Processing Architectures and Systems

Emulation and Simulation

Networking Applications 2

Poster Session 1

Poster Session 2

Poster Session 3

PhD Forum

Copyright © Sat May 16 23:12:43 2009 by Michael Ley (ley@uni-trier.de)