| 2008 |
|---|
| 11 | EE | F. Angarita,
Ma José Canet,
T. Sansaloni,
Javier Valls,
Vicenc Almenar-Terre:
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.
Signal Processing Systems 52(1): 35-44 (2008) |
| 10 | EE | F. Angarita,
Ma José Canet,
T. Sansaloni,
A. Perez-Pascual,
Javier Valls:
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN.
Signal Processing Systems 52(2): 181-191 (2008) |
| 2007 |
|---|
| 9 | EE | Roberto Gutierrez,
Javier Valls:
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.
FPL 2007: 472-475 |
| 8 | EE | T. Sansaloni,
A. Perez-Pascual,
V. Torres,
Javier Valls:
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.
VLSI Signal Processing 47(2): 183-187 (2007) |
| 2005 |
|---|
| 7 | | Elias Todorovich,
F. Angarita,
Javier Valls,
Eduardo I. Boemo:
Statistical Power Estimation for FPGA.
FPL 2005: 515-518 |
| 6 | | F. Angarita,
A. Perez-Pascual,
T. Sansaloni,
Javier Valls:
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.
FPL 2005: 535-538 |
| 2004 |
|---|
| 5 | EE | Elias Todorovich,
Eduardo I. Boemo,
F. Cardells,
Javier Valls:
Power analysis and estimation tool integrated with XPOWER.
FPGA 2004: 259 |
| 2003 |
|---|
| 4 | EE | T. Sansaloni,
Javier Valls,
Keshab K. Parhi:
Digit-Serial Complex-Number Multipliers on FPGAs.
VLSI Signal Processing 33(1-2): 105-115 (2003) |
| 2002 |
|---|
| 3 | EE | A. Perez-Pascual,
T. Sansaloni,
Javier Valls:
FPGA-based radix-4 butterflies for HIPERLAN/2.
ISCAS (3) 2002: 277-280 |
| 2 | EE | Javier Valls,
Martin Kuhlmann,
Keshab K. Parhi:
Evaluation of CORDIC Algorithms for FPGA Design.
VLSI Signal Processing 32(3): 207-222 (2002) |
| 1999 |
|---|
| 1 | EE | Javier Valls,
T. Sansaloni,
M. M. Peiro,
Eduardo I. Boemo:
Fast FPGA-based pipelined digit-serial/parallel multipliers.
ISCAS (1) 1999: 482-485 |
