| 2006 |
|---|
| 85 | | Reiner W. Hartenstein:
From Organic Computing to Reconfigurable Supercomputing.
ARCS Workshops 2006: 229- |
| 84 | EE | Carlos Morra,
M. Sackmann,
Sunil Shukla,
Jürgen Becker,
Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.
FPL 2006: 1-4 |
| 83 | EE | Reiner W. Hartenstein:
RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances.
IPDPS 2006 |
| 82 | EE | Peter Wintermayr,
Reiner W. Hartenstein,
Heinrich Meyr,
Steve Leibson:
Flexibility and low power: a contradiction in terms?
ISLPED 2006: 375 |
| 81 | | Carlos Morra,
M. Sackmann,
Jürgen Becker,
Reiner W. Hartenstein:
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures.
ReCoSoC 2006: 46-51 |
| 80 | EE | Reiner W. Hartenstein:
The re-definition of low power design for HPC: a paradigm shift.
SBCCI 2006: 7 |
| 79 | EE | Mauricio Ayala-Rincón,
Carlos H. Llanos,
Ricardo P. Jacobi,
Reiner W. Hartenstein:
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.
ACM Trans. Design Autom. Electr. Syst. 11(2): 251-281 (2006) |
| 2005 |
|---|
| 78 | | Carlos Morra,
Jürgen Becker,
Mauricio Ayala-Rincón,
Reiner W. Hartenstein:
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations.
FPL 2005: 25-30 |
| 2004 |
|---|
| 77 | EE | Reiner W. Hartenstein:
The digital divide of computing.
Conf. Computing Frontiers 2004: 357-362 |
| 76 | EE | Mauricio Ayala-Rincón,
Ricardo P. Jacobi,
Luis G. A. Carvalho,
Carlos H. Llanos,
Reiner W. Hartenstein:
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic.
SBCCI 2004: 248-253 |
| 75 | | Ricardo P. Jacobi,
Mauricio Ayala-Rincón,
Luis G. A. Carvalho,
Carlos H. Llanos,
Reiner W. Hartenstein:
Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming.
WOB 2004: 25-32 |
| 2003 |
|---|
| 74 | EE | Mauricio Ayala-Rincón,
R. Jacobi,
Carlos H. Llanos,
Reiner W. Hartenstein:
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing.
FDL 2003: 492-504 |
| 73 | EE | Reiner W. Hartenstein:
Are We Really Ready for the Breakthrough?
IPDPS 2003: 170 |
| 72 | EE | Mauricio Ayala-Rincón,
Rodrigo B. Nogueira,
Carlos H. Llanos,
Ricardo P. Jacobi,
Reiner W. Hartenstein:
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic.
SBCCI 2003: 205-210 |
| 71 | EE | Mauricio Ayala-Rincón,
Rodrigo B. Nogueira,
Carlos H. Llanos,
Ricardo P. Jacobi,
Reiner W. Hartenstein:
Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments.
SCCC 2003: 60- |
| 70 | EE | Jürgen Becker,
Reiner W. Hartenstein:
Configware and morphware going mainstream.
Journal of Systems Architecture 49(4-6): 127-142 (2003) |
| 2002 |
|---|
| 69 | EE | Reiner W. Hartenstein:
Disruptive Trends by Data-Stream-Based Computing.
FPL 2002: 4 |
| 68 | EE | Mauricio Ayala-Rincón,
Rinaldi Maya Neto,
Ricardo P. Jacobi,
Carlos H. Llanos,
Reiner W. Hartenstein:
Applying ELAN Strategies in Simulating Processors over Simple Architectures.
Electr. Notes Theor. Comput. Sci. 70(6): (2002) |
| 67 | EE | Mauricio Ayala-Rincón,
Reiner W. Hartenstein,
Rinaldi Maya Neto,
Ricardo P. Jacobi,
Carlos H. Llanos:
Architectural Specification, Exploration and Simulation Through Rewriting-Logic.
Revista Comlombiana de Computación 3(2): (2002) |
| 2001 |
|---|
| 66 | EE | Reiner W. Hartenstein:
Coarse grain reconfigurable architecture (embedded tutorial).
ASP-DAC 2001: 564-570 |
| 65 | EE | Reiner W. Hartenstein:
A decade of reconfigurable computing: a visionary retrospective.
DATE 2001: 642-649 |
| 64 | EE | Reiner W. Hartenstein:
Reconfigurable Computing: A New Business Model and its Impact on SoC Design.
DSD 2001: 103-111 |
| 2000 |
|---|
| 63 | | Reiner W. Hartenstein,
Herbert Grünbacher:
Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings
Springer 2000 |
| 62 | EE | Reiner W. Hartenstein,
Michael Herz,
Thomas Hoffmann,
Ulrich Nageldinger:
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array.
ASP-DAC 2000: 163-168 |
| 61 | EE | Reiner W. Hartenstein,
Michael Herz,
Thomas Hoffmann,
Ulrich Nageldinger:
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract).
FPGA 2000: 222 |
| 60 | EE | Reiner W. Hartenstein,
Michael Herz,
Thomas Hoffmann,
Ulrich Nageldinger:
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.
FPL 2000: 389-399 |
| 59 | EE | Reiner W. Hartenstein,
Thomas Hoffmann,
Ulrich Nageldinger:
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.
PATMOS 2000: 118-128 |
| 1999 |
|---|
| 58 | | Patrick Lysaght,
James Irvine,
Reiner W. Hartenstein:
Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings
Springer 1999 |
| 57 | | Reiner W. Hartenstein,
Michael Herz,
Ulrich Nageldinger,
Thomas Hoffmann:
An Internet Based Development Framework for Reconfigurable Computing.
FPL 1999: 155-164 |
| 56 | | Reiner W. Hartenstein,
Michael Herz,
Thomas Hoffmann,
Ulrich Nageldinger:
Mapping Applications onto Reconfigurable Kress Arrays.
FPL 1999: 385-390 |
| 55 | EE | Reiner W. Hartenstein,
Veljko M. Milutinovic:
Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction.
HICSS 1999 |
| 1998 |
|---|
| 54 | | Reiner W. Hartenstein,
Andres Keevallik:
Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings
Springer 1998 |
| 53 | | Jürgen Becker,
Reiner W. Hartenstein,
Michael Herz,
Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators.
ASP-DAC 1998: 23-33 |
| 52 | EE | Reiner W. Hartenstein,
Michael Herz,
Thomas Hoffmann,
Ulrich Nageldinger:
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators.
FPL 1998: 189-198 |
| 51 | EE | Reiner W. Hartenstein,
Michael Herz,
Frank Gilbert:
Designing for Xilinx XC6200 FPGAs.
FPL 1998: 29-38 |
| 50 | | Reiner W. Hartenstein,
Michael Herz,
Thomas Hoffmann,
Ulrich Nageldinger:
On Reconfigurable Co-processing Units.
IPPS/SPDP Workshops 1998: 67-72 |
| 49 | EE | Jürgen Becker,
Reiner W. Hartenstein:
Real-Time Prototyping in Microprocessor/Accelerator Symbiosis.
International Workshop on Rapid System Prototyping 1998: 32-38 |
| 1997 |
|---|
| 48 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Ulrich Nageldinger:
A Novel Universal Sequencer Hardware.
ARCS 1997: 143-152 |
| 47 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Ulrich Nageldinger:
A Novel Sequencer Hardware for Application Specific Computing.
ASAP 1997: 392-401 |
| 46 | EE | Reiner W. Hartenstein,
Jürgen Becker:
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators.
CODES 1997: 141-146 |
| 45 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Ulrich Nageldinger:
Data scheduling to increase performance of parallel accelerators.
FPL 1997: 294-303 |
| 44 | | Rainer Kress,
Reiner W. Hartenstein,
Ulrich Nageldinger:
An operating system for custom computing machines based on the Xputer paradigm.
FPL 1997: 304-313 |
| 43 | EE | Reiner W. Hartenstein,
Jürgen Becker:
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators.
HICSS (5) 1997: 125-134 |
| 42 | EE | Reiner W. Hartenstein,
Jürgen Becker:
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators.
VLSI Design 1997: 146-150 |
| 41 | | William H. Mangione-Smith,
Brad Hutchins,
David L. Andrews,
André DeHon,
Carl Ebeling,
Reiner W. Hartenstein,
Oskar Mencer,
John Morris,
Krishna V. Palem,
Viktor K. Prasanna,
Henk A. E. Spaanenburg:
Seeking Solutions in Configurable Computing.
IEEE Computer 30(12): 38-43 (1997) |
| 1996 |
|---|
| 40 | | Reiner W. Hartenstein,
Manfred Glesner:
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings
Springer 1996 |
| 39 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Rainer Kress,
Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures.
ASAP 1996: 274-283 |
| 38 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress:
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine.
CODES 1996: 77-84 |
| 37 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress:
Two-Level Hardware/Software Partitioning Using CoDe-X.
ECBS 1996: 395- |
| 36 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress:
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view.
FPL 1996: 65-76 |
| 35 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Rainer Kress,
Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture.
IPPS 1996: 544-548 |
| 34 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress,
Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework.
VLSI Design 1996: 81-84 |
| 33 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress,
Helmut Reinig:
High-performance computing using a reconfigurable accelerator.
Concurrency - Practice and Experience 8(6): 429-443 (1996) |
| 1995 |
|---|
| 32 | EE | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress,
Helmut Reinig,
Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine.
ASAP 1995: 129-132 |
| 31 | EE | Reiner W. Hartenstein,
Rainer Kress:
A datapath synthesis system for the reconfigurable datapath architecture.
ASP-DAC 1995 |
| 30 | EE | Reiner W. Hartenstein,
Karin Schmidt:
Combining structural and procedural programming by parallelizing compilation.
SAC 1995: 130-134 |
| 29 | | Reiner W. Hartenstein:
Custom Computing Machines - Das aktuelle Schlagwort
Informatik Spektrum 18(4): 228-229 (1995) |
| 28 | | Reiner W. Hartenstein:
Hardware/Software Co-Design - Das aktuelle Schlagwort
Informatik Spektrum 18(5): 286-287 (1995) |
| 1994 |
|---|
| 27 | | Reiner W. Hartenstein,
Michal Servít:
Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings
Springer 1994 |
| 26 | | Reiner W. Hartenstein,
Rainer Kress,
Helmut Reinig:
A New FPGA Architecture for Word-Oriented Datapaths.
FPL 1994: 144-155 |
| 25 | | Andreas Ast,
Jürgen Becker,
Reiner W. Hartenstein,
Rainer Kress,
Helmut Reinig,
Karin Schmidt:
Data-Procedural Languages for FPL-based Machines.
FPL 1994: 183-195 |
| 1993 |
|---|
| 24 | | Herbert Grünbacher,
Reiner W. Hartenstein:
Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers
Springer 1993 |
| 1992 |
|---|
| 23 | | J. Bloedel,
M. Brandstetter,
Peter Conradi,
W. Drangmeister,
Reiner W. Hartenstein,
D. Schroeder:
An Information Model Describing the Exchange of IC Technology Data.
Electronic Design Automation Frameworks 1992: 9-19 |
| 22 | | Andreas Ast,
Reiner W. Hartenstein,
Rainer Kress,
Helmut Reinig,
Karin Schmidt:
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods.
FPL 1992: 211-217 |
| 1991 |
|---|
| 21 | | Franz-Josef Brandenburg,
Werner Freise,
Winfried Görke,
Reiner W. Hartenstein,
P. Kühn,
H. J. Schmitt:
Gemeinsame Stellungnahme der Fakultätentage Elektrotechnik und Informatik zur Abstimmung ihrer Fachgebierte im Bereich Informationstechnik.
Informatik Spektrum 14(3): 163-167 (1991) |
| 1990 |
|---|
| 20 | | Reiner W. Hartenstein,
Alexander G. Hirschbiel,
M. Weber:
Xputers: An Open Family of Non-Von Neumann Architectures.
ARCS 1990: 45-58 |
| 19 | | Reiner W. Hartenstein,
Alexander G. Hirschbiel,
M. Weber:
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware.
CONPAR 1990: 51-62 |
| 18 | | Reiner W. Hartenstein,
Alexander G. Hirschbiel,
M. Riedmüller,
Karin Schmidt,
M. Weber:
Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing.
DAGM-Symposium 1990: 404-417 |
| 17 | | Reiner W. Hartenstein,
Alexander G. Hirschbiel,
M. Weber:
The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration.
ICPP (1) 1990: 609-610 |
| 1988 |
|---|
| 16 | | Reiner W. Hartenstein,
Michael Ryba:
Partitionierungsschemata für Rechnerstrukturen.
GI Jahrestagung (2) 1988: 246-262 |
| 15 | | Reiner W. Hartenstein,
K. W. Jörg,
U. Welters:
MLED - Ein Mehrebenen Graphik Editor für den VLSI-Entwurf.
GI Jahrestagung (2) 1988: 281-288 |
| 14 | | Gerold Affs,
Reiner W. Hartenstein,
Andrea Wodtko:
The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions.
ITC 1988: 230-235 |
| 1987 |
|---|
| 13 | | Reiner W. Hartenstein,
U. Welters:
Mehrebenenen-Graphik-Editor MLED als DBMS für VLSI-Simulation.
Simulationstechnik 1987: 250-257 |
| 1983 |
|---|
| 12 | | Reiner W. Hartenstein:
Silicon Compiler - Das aktuelle Schlagwort.
Informatik Spektrum 6(4): 223-224 (1983) |
| 1982 |
|---|
| 11 | | Reiner W. Hartenstein:
Die "Neue Mikroelektronik" in der Informatik: Voraussetzungen und Auswirkungen.
GI Jahrestagung 1982: 30-44 |
| 10 | | Reiner W. Hartenstein:
KARL-II - eine Sprache zur Spezifikation beim Entwurf Kundenspezifischer Digitalbausteine.
Angewandte Informatik 24(12): 581-591 (1982) |
| 1981 |
|---|
| 9 | | Reiner W. Hartenstein:
VLSI-Algorithmen - Das aktuelle Schlagwort.
Informatik Spektrum 4(2): 124 (1981) |
| 1980 |
|---|
| 8 | | Reiner W. Hartenstein,
Peter Liell:
Ein Compiler für die Register Transfer-Sprache KARL-2.
GI Jahrestagung 1980: 559 |
| 7 | | J. Dieckmann,
Reiner W. Hartenstein,
Werner Konrad:
Software-Zuverlässigkeit mit Rechnernetz-Baukästen verteilter Programmierung.
Hardware für Software 1980: 188-197 |
| 6 | | Reiner W. Hartenstein:
VLSI-Bausteine in geringen Stückzahlen für Spezial-Anwendungen.
Elektronische Rechenanlagen 22(4): 159-173 (1980) |
| 1974 |
|---|
| 5 | | Reiner W. Hartenstein:
Konzepte der Mikroprogrammierung.
ARCS 1974: 22-42 |
| 1973 |
|---|
| 4 | | Reiner W. Hartenstein:
Hierarchy of Interpreters for Modelling Complex Digital Systems.
GI Jahrestagung 1973: 261-269, 508 |
| 3 | | Reiner W. Hartenstein:
Increasing Hardware Complexity - A Challenge to Computer Architecture Education.
ISCA 1973: 201-206 |
| 1971 |
|---|
| 2 | | Reiner W. Hartenstein:
Synthese endlicher Automaten bei Problemen der Erkennung, Klassifikation und Informationsreduktion.
Elektronische Informationsverarbeitung und Kybernetik 7(5/6): 331-353 (1971) |
| 1970 |
|---|
| 1 | | Reiner W. Hartenstein:
Suchlistenstrukturen zur Darstellung gerichteter Graphen und deren Anwendung bei Synthese und Minimierung spezieller endlicher Automaten.
Elektronische Rechenanlagen 12(4): 208-216 (1970) |
