| |
| 2005 | ||
|---|---|---|
| 1 | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304 | |
| 1 | Laurent Fesquet | [1] |
| 2 | Jerome Quartana | [1] |
| 3 | Salim Renane | [1] |
| 4 | Marc Renaudin | [1] |