| 2006 |
|---|
| 5 | EE | Francisco-Javier Veredas,
Michael Scheppler,
Hans-Jörg Pfleiderer:
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.
DATE Designers' Forum 2006: 36-41 |
| 4 | EE | Francisco-Javier Veredas,
Michael Scheppler,
Bumei Zhai,
Hans-Jörg Pfleiderer:
LUT-based MPGAs for fast turnaround time conversion flow.
ISCAS 2006 |
| 3 | EE | Francisco-Javier Veredas,
Michael Scheppler,
Bumei Zhai,
Hans-Jörg Pfleiderer:
Regular Routing Architecture for a LUT-based MPGA.
ISVLSI 2006: 257-262 |
| 2005 |
|---|
| 2 | | Francisco-Javier Veredas,
Michael Scheppler,
Will Moffat,
Bingfeng Mei:
Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.
FPL 2005: 106-111 |
| 2003 |
|---|
| 1 | EE | Markus Hütter,
Holger Bock,
Michael Scheppler:
A New Reconfigurable Architecture for Single Cycle Context Switching.
IPDPS 2003: 186 |
