| 2008 |
|---|
| 7 | EE | Carlos Morra,
João Bispo,
João M. P. Cardoso,
Jürgen Becker:
Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.
FCCM 2008: 320-321 |
| 6 | EE | Carlos Morra,
João M. P. Cardoso,
João Bispo,
Jürgen Becker:
Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.
SASP 2008: 34-41 |
| 2007 |
|---|
| 5 | EE | Carlos Morra,
João M. P. Cardoso,
Jürgen Becker:
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.
IPDPS 2007: 1-8 |
| 2006 |
|---|
| 4 | EE | Carlos Morra:
Configware Design Space Exploration Using Rewriting Logic.
FPL 2006: 1-2 |
| 3 | EE | Carlos Morra,
M. Sackmann,
Sunil Shukla,
Jürgen Becker,
Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.
FPL 2006: 1-4 |
| 2 | | Carlos Morra,
M. Sackmann,
Jürgen Becker,
Reiner W. Hartenstein:
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures.
ReCoSoC 2006: 46-51 |
| 2005 |
|---|
| 1 | | Carlos Morra,
Jürgen Becker,
Mauricio Ayala-Rincón,
Reiner W. Hartenstein:
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations.
FPL 2005: 25-30 |
