2009 |
9 | EE | Kazuki Inoue,
Motoki Amagasaki,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Local Interconnect Architecture for Variable Grain Logic Cell.
ARC 2009: 97-109 |
2007 |
8 | EE | Kazunori Matsuyama,
Motoki Amagasaki,
Hideaki Nakayama,
Ryoichi Yamaguchi,
Masahiro Iida,
Toshinori Sueyoshi:
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.
ARC 2007: 142-154 |
7 | EE | Hiroshi Shinohara,
Hideaki Monji,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.
FCCM 2007: 285-286 |
6 | EE | Hiroshi Shinohara,
Hideaki Monji,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.
FCCM 2007: 309-310 |
5 | EE | Motoki Amagasaki,
Ryoichi Yamaguchi,
Kazunori Matsuyama,
Masahiro Iida,
Toshinori Sueyoshi:
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores.
FPL 2007: 550-553 |
4 | EE | Hiroshi Shinohara,
Hideaki Monji,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices.
IEICE Transactions 90-D(12): 1986-1989 (2007) |
2006 |
3 | EE | Masaki Kobata,
Masahiro Iida,
Toshinori Sueyoshi:
Effective clustering technique to optimize routability of outer cluster nets.
FPGA 2006: 229 |
2 | EE | Motoki Amagasaki,
Takurou Shimokawa,
Kazunori Matsuyama,
Ryoichi Yamaguchi,
Hideaki Nakayama,
Naoto Hamabe,
Masahiro Iida,
Toshinori Sueyoshi:
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.
VLSI-SoC 2006: 198-203 |
2005 |
1 | | Hisashi Tsukiashi,
Masahiro Iida,
Toshinori Sueyoshi:
Applying the Small-World Network to Routing Structure of FPGAs.
FPL 2005: 65-70 |