2007 |
38 | EE | John Wawrzynek:
Adventures with a Reconfigurable Research Platform.
FPL 2007: 3 |
37 | EE | Alex Krasnov,
Andrew Schultz,
John Wawrzynek,
Greg Gibeling,
Pierre-Yves Droz:
RAMP Blue: A Message-Passing Manycore System in FPGAs.
FPL 2007: 54-61 |
36 | EE | John Wawrzynek,
David A. Patterson,
Mark Oskin,
Shih-Lien Lu,
Christoforos E. Kozyrakis,
James C. Hoe,
Derek Chiou,
Krste Asanovic:
RAMP: Research Accelerator for Multiple Processors.
IEEE Micro 27(2): 46-57 (2007) |
2006 |
35 | EE | André DeHon,
Randy Huang,
John Wawrzynek:
Stochastic spatial routing for reconfigurable networks.
Microprocessors and Microsystems 30(6): 301-318 (2006) |
34 | EE | André DeHon,
Yury Markovskiy,
Eylon Caspi,
Michael Chu,
Randy Huang,
Stylianos Perissakis,
Laura Pozzi,
Joseph Yeh,
John Wawrzynek:
Stream computations organized for reconfigurable execution.
Microprocessors and Microsystems 30(6): 334-354 (2006) |
2005 |
33 | | Chen Chang,
John Wawrzynek,
Pierre-Yves Droz,
Robert W. Brodersen:
The Design And Application Of A High-End Reconfigurable Computing System.
ERSA 2005: 129-136 |
32 | | Zohair Hyder,
John Wawrzynek:
Defect Tolerance in Multiple-FPGA Systems.
FPL 2005: 247-254 |
31 | EE | Chen Chang,
John Wawrzynek,
Robert W. Brodersen:
BEE2: A High-End Reconfigurable Computing System.
IEEE Design & Test of Computers 22(2): 114-125 (2005) |
2004 |
30 | EE | Nicholas Weaver,
John R. Hauser,
John Wawrzynek:
The SFRA: a corner-turn FPGA architecture.
FPGA 2004: 3-12 |
2003 |
29 | EE | Nicholas Weaver,
Yury Markovskiy,
Yatish Patel,
John Wawrzynek:
Post-placement C-slow retiming for the xilinx virtex FPGA.
FPGA 2003: 185-194 |
28 | EE | Randy Huang,
John Wawrzynek,
André DeHon:
Stochastic, spatial routing for hypergraphs, trees, and meshes.
FPGA 2003: 78-87 |
27 | EE | John Wawrzynek,
Keith Diefendorff:
Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics.
IEEE Micro 23(2): 8-11 (2003) |
2002 |
26 | EE | André DeHon,
Randy Huang,
John Wawrzynek:
Hardware-Assisted Fast Routing.
FCCM 2002: 205- |
25 | EE | Nicholas Weaver,
John Wawrzynek:
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks.
FCCM 2002: 303- |
24 | EE | Yury Markovskiy,
Eylon Caspi,
Randy Huang,
Joseph Yeh,
Michael Chu,
John Wawrzynek,
André DeHon:
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.
FPGA 2002: 196-205 |
2001 |
23 | EE | John Lazzaro,
John Wawrzynek:
A case for network musical performance.
NOSSDAV 2001: 157-166 |
2000 |
22 | | Nicholas Weaver,
John Wawrzynek:
A Comparison of the AES Candidates Amenability to FPGA Implementation.
AES Candidate Conference 2000: 28-39 |
21 | EE | Timothy J. Callahan,
John Wawrzynek:
Adapting software pipelining for reconfigurable computing.
CASES 2000: 57-64 |
20 | EE | Eylon Caspi,
Michael Chu,
Randy Huang,
Joseph Yeh,
John Wawrzynek,
André DeHon:
Stream Computations Organized for Reconfigurable Execution (SCORE).
FPL 2000: 605-614 |
19 | | Timothy J. Callahan,
John R. Hauser,
John Wawrzynek:
The Garp Architecture and C Compiler.
IEEE Computer 33(4): 62-69 (2000) |
1999 |
18 | EE | André DeHon,
John Wawrzynek:
Reconfigurable Computing: What, Why, and Implications for Design Automation.
DAC 1999: 610-615 |
17 | EE | William Tsu,
Kip Macy,
Atul Joshi,
Randy Huang,
Norman Walker,
Tony Tung,
Omid Rowhani,
George Varghese,
John Wawrzynek,
André DeHon:
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array.
FPGA 1999: 125-134 |
16 | | John Lazzaro,
John Wawrzynek:
JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure.
Neural Computation 11(1): 267-296 (1999) |
1998 |
15 | EE | Michael Chu,
Nicholas Weaver,
Kolja Sulimma,
André DeHon,
John Wawrzynek:
Object Oriented Circuit-Generators in Java.
FCCM 1998: 158-166 |
14 | EE | Timothy J. Callahan,
Philip Chong,
André DeHon,
John Wawrzynek:
Fast Module Mapping and Placement for Datapaths in FPGAs.
FPGA 1998: 123-132 |
13 | EE | Timothy J. Callahan,
John Wawrzynek:
Instruction-Level Parallelism for Reconfigurable Computing.
FPL 1998: 248-257 |
1997 |
12 | EE | John R. Hauser,
John Wawrzynek:
Garp: a MIPS processor with a reconfigurable coprocessor.
FCCM 1997: 12-21 |
11 | EE | Timothy J. Callahan,
John Wawrzynek:
Datapath-oriented FPGA mapping and placement for configurable computing.
FCCM 1997: 234-235 |
1996 |
10 | EE | John Lazzaro,
John Wawrzynek,
Richard Lippmann:
A Micropower Analog VLSI HMM State Decoder for Wordspotting.
NIPS 1996: 727-733 |
9 | | John Wawrzynek,
Krste Asanovic,
Brian Kingsbury,
David Johnson,
James Beck,
Nelson Morgan:
Spert-II: A Vector Microprocessor System.
IEEE Computer 29(3): 79-86 (1996) |
1995 |
8 | EE | John Lazzaro,
John Wawrzynek:
A multi-sender asynchronous extension to the AER protocol.
ARVLSI 1995: 158-171 |
7 | EE | John Wawrzynek,
Krste Asanovic,
Brian Kingsbury,
James Beck,
David Johnson,
Nelson Morgan:
SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training.
NIPS 1995: 619-625 |
6 | EE | John Lazzaro,
John Wawrzynek:
Silicon Models for Auditory Scene Analysis.
NIPS 1995: 699-705 |
1993 |
5 | EE | Krste Asanovic,
James Beck,
Jerry Feldman,
Nelson Morgan,
John Wawrzynek:
Designing A Connectionist Network Supercomputer.
Int. J. Neural Syst. 4(4): 317-326 (1993) |
4 | EE | Krste Asanovic,
Nelson Morgan,
John Wawrzynek:
Using simulations of reduced precision arithmetic to design a neuro-microprocessor.
VLSI Signal Processing 6(1): 33-44 (1993) |
1992 |
3 | EE | John Lazzaro,
John Wawrzynek,
Misha Mahowald,
Massimo Sivilotti,
Dave Gillespie:
Silicon Auditory Processors as Computer Peripherals.
NIPS 1992: 820-827 |
1991 |
2 | | David E. Culler,
Anurag Sah,
Klaus E. Schauser,
Thorsten von Eicken,
John Wawrzynek:
Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine.
ASPLOS 1991: 164-175 |
1 | EE | Paul de Dood,
John Wawrzynek,
Erwin Liu,
Roberto Suaya:
A Two-Dimensional Topological Compactor With Octagonal Geometry.
DAC 1991: 727-731 |