| 2008 |
|---|
| 5 | EE | Tomas Pecenka,
Lukás Sekanina,
Zdenek Kotásek:
Evolution of synthetic RTL benchmark circuits with predefined testability.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 2006 |
|---|
| 4 | | Tomas Pecenka,
Zdenek Kotásek,
Lukás Sekanina:
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.
DDECS 2006: 285-289 |
| 3 | EE | Tomas Pecenka,
Josef Strnadel,
Zdenek Kotásek,
Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters.
DSD 2006: 504-514 |
| 2005 |
|---|
| 2 | EE | Tomas Pecenka,
Zdenek Kotásek,
Lukás Sekanina,
Josef Strnadel:
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.
Evolvable Hardware 2005: 51-58 |
| 1 | | Martin Zádník,
Tomas Pecenka,
Jan Korenek:
NetFlow Probe Intended for High-Speed Networks.
FPL 2005: 695-698 |
