2008 |
13 | EE | Jason Lee,
Lesley Shannon,
Matthew J. Yedlin,
Gary F. Margrave:
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator.
ASAP 2008: 197-202 |
12 | EE | David Dickin,
Lesley Shannon:
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms.
ASAP 2008: 67-72 |
11 | EE | Edward Chen,
William A. Gruver,
Dorian Sabaz,
Lesley Shannon:
Facilitating Processor-Based DPR Systems for non-DPR Experts.
FCCM 2008: 318-319 |
2007 |
10 | EE | Lesley Shannon,
Paul Chow:
SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse.
IEEE Trans. VLSI Syst. 15(4): 377-390 (2007) |
9 | EE | Manuel Saldaña,
Lesley Shannon,
Jia Shuo Yue,
Sikang Bian,
John Craig,
Paul Chow:
Routability of Network Topologies in FPGAs.
IEEE Trans. VLSI Syst. 15(8): 948-951 (2007) |
2006 |
8 | EE | Manuel Saldaña,
Lesley Shannon,
Paul Chow:
The routability of multiprocessor network topologies in FPGAs.
FPGA 2006: 232 |
7 | EE | Lesley Shannon,
Blair Fort,
Samir Parikh,
Arun Patel,
Manuel Saldaña,
Paul Chow:
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
FPL 2006: 1-6 |
6 | EE | Manuel Saldaña,
Lesley Shannon,
Paul Chow:
The routability of multiprocessor network topologies in FPGAs.
SLIP 2006: 49-56 |
2005 |
5 | EE | Lesley Shannon,
Paul Chow:
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller.
FCCM 2005: 63-72 |
4 | | Lesley Shannon,
Paul Chow:
Leveraging Reconfigurability in the Design Process.
FPL 2005: 731-732 |
3 | | Lesley Shannon,
Blair Fort,
Samir Parikh,
Arun Patel,
Manuel Saldaña,
Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface.
FPT 2005: 341-342 |
2004 |
2 | EE | Lesley Shannon,
Paul Chow:
Using reconfigurability to achieve real-time profiling for hardware/software codesign.
FPGA 2004: 190-199 |
2003 |
1 | EE | Lesley Shannon,
Paul Chow:
Standardizing the Performance Assessment of Reconfigurable Processor Architectures.
FCCM 2003: 282-283 |