| 2007 |
|---|
| 5 | EE | Premysl Sucha,
Zdenek Hanzálek,
Antonin Hermanek,
Jan Schier:
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm.
VLSI Signal Processing 46(1): 35-53 (2007) |
| 2006 |
|---|
| 4 | EE | Premysl Sucha,
Zdenek Hanzálek:
Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs.
IPDPS 2006: 1-8 |
| 3 | EE | Premysl Sucha,
Zdenek Hanzálek:
Scheduling of tasks with precedence delays and relative deadlines framework for time-optimal dynamic reconfiguration of FPGAs.
IPDPS 2006 |
| 2005 |
|---|
| 2 | | Zdenek Pohl,
Premysl Sucha,
Jiri Kadlec,
Zdenek Hanzálek:
Performance Tuning of Iterative Algorithms in Signal Processing.
FPL 2005: 699-702 |
| 2004 |
|---|
| 1 | EE | Premysl Sucha,
Zdenek Pohl,
Zdenek Hanzálek:
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit.
IEEE Real-Time and Embedded Technology and Applications Symposium 2004: 404-412 |
