| 2008 |
|---|
| 11 | EE | Alexander Danilin,
Martijn T. Bennebroek,
Sergei Sawitzki:
A Novel Routing Architecture for Field-Programmable Gate-Arrays.
ARCS 2008: 144-158 |
| 10 | EE | Kees Goossens,
Martijn T. Bennebroek,
Jae Young Hur,
Muhammad Aqeel Wahlah:
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.
NOCS 2008: 45-54 |
| 2007 |
|---|
| 9 | EE | Bart Vermeulen,
Kees Goossens,
Remco van Steeden,
Martijn T. Bennebroek:
Communication-Centric SoC Debug Using Transactions.
European Test Symposium 2007: 69-76 |
| 8 | EE | Martijn T. Bennebroek,
Alexander Danilin:
Multiplexer-based routing fabric for reconfigurable logic.
FPL 2007: 463-466 |
| 7 | EE | Kees Goossens,
Bart Vermeulen,
Remco van Steeden,
Martijn T. Bennebroek:
Transaction-Based Communication-Centric Debug.
NOCS 2007: 95-106 |
| 2006 |
|---|
| 6 | EE | Maurice Meijer,
Rohini Krishnan,
Martijn T. Bennebroek:
Energy-efficient FPGA interconnect design.
DATE Designers' Forum 2006: 42-47 |
| 5 | EE | Alexander Danilin,
Martijn T. Bennebroek,
Sergei Sawitzki:
Astra: An Advanced Space-Time Reconfigurable Architecture.
FPL 2006: 1-4 |
| 2005 |
|---|
| 4 | | Alexander Danilin,
Martijn T. Bennebroek,
Sergei Sawitzki:
A Novel Toolset for the Development of FPGA-like Reconfigurable Logic.
FPL 2005: 640-643 |
| 2004 |
|---|
| 3 | EE | Rohini Krishnan,
José Pineda de Gyvez,
Martijn T. Bennebroek:
Low energy FPGA interconnect design.
ACM Great Lakes Symposium on VLSI 2004: 393-396 |
| 2 | EE | Rohini Krishnan,
José Pineda de Gyvez,
Martijn T. Bennebroek:
Low energy FPGA interconnect design.
FPGA 2004: 255 |
| 2003 |
|---|
| 1 | EE | Martijn T. Bennebroek:
Validation of wire length distribution models on commercial designs.
SLIP 2003: 41 |
