2009 |
20 | EE | Yoshihiro Ichinomiya,
Shiro Tanoue,
Tomoyuki Ishida,
Motoki Amagasaki,
Morihiro Kuga,
Toshinori Sueyoshi:
Memory Sharing Approach for TMR Softcore Processor.
ARC 2009: 268-274 |
19 | EE | Kazuki Inoue,
Motoki Amagasaki,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Local Interconnect Architecture for Variable Grain Logic Cell.
ARC 2009: 97-109 |
2008 |
18 | EE | Takuo Nakashima,
Toshinori Sueyoshi:
Analysis of Queueing Property for Self-Similar Traffic.
AINA 2008: 241-248 |
17 | EE | Takuo Nakashima,
Shunsuke Oshima,
Yusuke Nishikido,
Toshinori Sueyoshi:
Extraction of Characteristics of Anomaly Accessed IP Packets by the Entropy-Based Analysis.
CISIS 2008: 141-147 |
2007 |
16 | EE | Takuo Nakashima,
Toshinori Sueyoshi:
Self-Similar Property for TCP Traffic under the Bottleneck Restrainment.
AINA Workshops (1) 2007: 228-233 |
15 | EE | Kazunori Matsuyama,
Motoki Amagasaki,
Hideaki Nakayama,
Ryoichi Yamaguchi,
Masahiro Iida,
Toshinori Sueyoshi:
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.
ARC 2007: 142-154 |
14 | EE | Takuo Nakashima,
Toshinori Sueyoshi:
Performance Estimation of TCP under SYN Flood Attacks.
CISIS 2007: 92-99 |
13 | EE | Hiroshi Shinohara,
Hideaki Monji,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.
FCCM 2007: 285-286 |
12 | EE | Hiroshi Shinohara,
Hideaki Monji,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.
FCCM 2007: 309-310 |
11 | EE | Motoki Amagasaki,
Ryoichi Yamaguchi,
Kazunori Matsuyama,
Masahiro Iida,
Toshinori Sueyoshi:
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores.
FPL 2007: 550-553 |
10 | EE | Toshinori Sueyoshi:
Special Section on Reconfigurable Systems.
IEICE Transactions 90-D(12): 1903-1904 (2007) |
9 | EE | Hiroshi Shinohara,
Hideaki Monji,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices.
IEICE Transactions 90-D(12): 1986-1989 (2007) |
2006 |
8 | EE | Masaki Kobata,
Masahiro Iida,
Toshinori Sueyoshi:
Effective clustering technique to optimize routability of outer cluster nets.
FPGA 2006: 229 |
7 | EE | Motoki Amagasaki,
Takurou Shimokawa,
Kazunori Matsuyama,
Ryoichi Yamaguchi,
Hideaki Nakayama,
Naoto Hamabe,
Masahiro Iida,
Toshinori Sueyoshi:
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.
VLSI-SoC 2006: 198-203 |
2005 |
6 | | Hisashi Tsukiashi,
Masahiro Iida,
Toshinori Sueyoshi:
Applying the Small-World Network to Routing Structure of FPGAs.
FPL 2005: 65-70 |
2002 |
5 | EE | Toshinori Sueyoshi,
Morihiro Kuga,
Hidetomo Shibamura:
KITE microprocessor and CAE for computer science.
Systems and Computers in Japan 33(8): 64-74 (2002) |
2001 |
4 | EE | Yulu Yang,
Akira Funahashi,
Akiya Jouraku,
Hiroaki Nishi,
Hideharu Amano,
Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
IEEE Trans. Parallel Distrib. Syst. 12(7): 701-715 (2001) |
1993 |
3 | | Yulu Yang,
Hideharu Amano,
Hidetomo Shibamura,
Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
SPDP 1993: 591-595 |
1989 |
2 | EE | Kazuaki Murakami,
Shin-ichiro Mori,
Akira Fukuda,
Toshinori Sueyoshi,
Shinji Tomita:
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.
ICS 1989: 351-360 |
1 | | Kazuaki Murakami,
Shin-ichiro Mori,
Akira Fukuda,
Toshinori Sueyoshi,
Shinji Tomita:
The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture.
IFIP Congress 1989: 995-1000 |