| 2008 |
|---|
| 10 | EE | John N. Coleman,
Christopher I. Softley,
Jiri Kadlec,
Rudolf Matousek,
Milan Tichý,
Zdenek Pohl,
Antonin Hermanek,
Nico F. Benschop:
The European Logarithmic Microprocesor.
IEEE Trans. Computers 57(4): 532-546 (2008) |
| 2007 |
|---|
| 9 | EE | Zdenek Pohl,
Milan Tichý:
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.
FPL 2007: 774-777 |
| 2005 |
|---|
| 8 | EE | Kelly Nasi,
Martin Danek,
Theodoros Karoubalis,
Zdenek Pohl:
Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only).
FPGA 2005: 262 |
| 7 | | Kelly Nasi,
Martin Danek,
Theodoros Karoubalis,
Zdenek Pohl:
Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration.
FPL 2005: 590-593 |
| 6 | | Zdenek Pohl,
Premysl Sucha,
Jiri Kadlec,
Zdenek Hanzálek:
Performance Tuning of Iterative Algorithms in Signal Processing.
FPL 2005: 699-702 |
| 2004 |
|---|
| 5 | EE | Premysl Sucha,
Zdenek Pohl,
Zdenek Hanzálek:
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit.
IEEE Real-Time and Embedded Technology and Applications Symposium 2004: 404-412 |
| 2003 |
|---|
| 4 | EE | Zdenek Pohl,
Rudolf Matousek,
Jiri Kadlec,
Milan Tichý,
Miroslav Lícko:
Lattice adaptive filter implementation for FPGA.
FPGA 2003: 246 |
| 3 | EE | Antonin Hermanek,
Zdenek Pohl,
Jiri Kadlec:
FPGA Implementation of the Adpaptive Lattice Filter.
FPL 2003: 1095-1098 |
| 2 | EE | Zdenek Pohl,
Jan Schier,
Miroslav Lícko,
Antonin Hermanek,
Milan Tichý,
Rudolf Matousek,
Jiri Kadlec:
Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping.
IPDPS 2003: 190 |
| 2002 |
|---|
| 1 | EE | Rudolf Matousek,
Milan Tichý,
Zdenek Pohl,
Jiri Kadlec,
Christopher I. Softley,
Nick Coleman:
Logarithmic Number System and Floating-Point Arithmetics on FPGA.
FPL 2002: 627-636 |
