Marta Portela-García

2009
11	EE	Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García: SET Emulation Under a Quantized Delay Model. J. Electronic Testing 25(1): 107-116 (2009)
2007
10	EE	Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena: SET Emulation Under a Quantized Delay Model. DFT 2007: 68-77
9	EE	Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena: A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. IOLTS 2007: 101-106
8	EE	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation CoRR abs/0710.4757: (2007)
2006
7		Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes: An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. DDECS 2006: 218-219
6	EE	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82
5	EE	Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena: Emulation-based Fault Injection in Circuits with Embedded Memories. IOLTS 2006: 183-184
2005
4	EE	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. DATE 2005: 308-309
3		Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. FPL 2005: 397-402
2	EE	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. IOLTS 2005: 43-48
2004
1	EE	Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena: Transient Fault Emulation of Hardened Circuits in FPGA Platforms. IOLTS 2004: 109-114

Coauthor Index

1	Raúl Fernández Cardenal	[10] [11]
2	Luis Entrena (Luis Entrena-Arrontes)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
3	Mario García-Valderas	[1] [2] [3] [4] [5] [7] [8] [9] [10] [11]
4	Celia López-Ongil (Celia López)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
5	Matteo Sonza Reorda	[6]
6	Luca Sterpone	[6]
7	Massimo Violante	[6]