| 2006 |
|---|
| 17 | EE | J. Gonzalez-Gomez,
Ivan Gonzalez,
Francisco J. Gomez-Arribas,
Eduardo I. Boemo:
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors.
ARC 2006: 24-29 |
| 16 | EE | Elias Todorovich,
Eduardo I. Boemo:
A-B Nodes Classification for Power Estimation.
FPL 2006: 1-6 |
| 2005 |
|---|
| 15 | | Elias Todorovich,
F. Angarita,
Javier Valls,
Eduardo I. Boemo:
Statistical Power Estimation for FPGA.
FPL 2005: 515-518 |
| 2004 |
|---|
| 14 | EE | Elias Todorovich,
Eduardo I. Boemo,
F. Cardells,
Javier Valls:
Power analysis and estimation tool integrated with XPOWER.
FPGA 2004: 259 |
| 13 | EE | Sergio López-Buedo,
Eduardo I. Boemo:
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report.
FPGA 2004: 79-86 |
| 12 | EE | Gustavo Sutter,
Jean-Pierre Deschamps,
Gery Bioul,
Eduardo I. Boemo:
Power Aware Dividers in FPGA.
PATMOS 2004: 574-584 |
| 11 | EE | C. M. Gonzalez,
H. A. Larrondo,
C. A. Gayoso,
L. J. Arnone,
Eduardo I. Boemo:
Digital Signal Transmission with Chaotic Encryption: Design and Evaluation of a FPGA Realization
CoRR cs.CR/0402056: (2004) |
| 2002 |
|---|
| 10 | EE | Sergio López-Buedo,
Paula Riviere,
Pablo Pernas,
Eduardo I. Boemo:
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology.
FPL 2002: 162-170 |
| 9 | EE | Elias Todorovich,
M. Gilabert,
Gustavo Sutter,
Sergio López-Buedo,
Eduardo I. Boemo:
A Tool for Activity Estimation in FPGAs.
FPL 2002: 340-349 |
| 8 | EE | Gustavo Sutter,
Elias Todorovich,
Sergio López-Buedo,
Eduardo I. Boemo:
FSM Decomposition for Low Power in FPGA.
FPL 2002: 350-359 |
| 7 | EE | Gustavo Sutter,
Elias Todorovich,
Sergio López-Buedo,
Eduardo I. Boemo:
Low-Power FSMs in FPGA: Encoding Alternatives.
PATMOS 2002: 363-370 |
| 2000 |
|---|
| 6 | EE | Sergio López-Buedo,
Javier Garrido,
Eduardo I. Boemo:
Thermal Testing on Reconfigurable Computers.
IEEE Design & Test of Computers 17(1): 84-91 (2000) |
| 1999 |
|---|
| 5 | EE | Javier Valls,
T. Sansaloni,
M. M. Peiro,
Eduardo I. Boemo:
Fast FPGA-based pipelined digit-serial/parallel multipliers.
ISCAS (1) 1999: 482-485 |
| 1998 |
|---|
| 4 | EE | Eduardo I. Boemo,
Sergio López-Buedo,
Juan M. Meneses:
Some experiments about wave pipelining on FPGA's.
IEEE Trans. VLSI Syst. 6(2): 232-237 (1998) |
| 1997 |
|---|
| 3 | | Eduardo I. Boemo,
Sergio López-Buedo:
Thermal monitoring on FPGAs using ring-oscillators.
FPL 1997: 69-78 |
| 1996 |
|---|
| 2 | EE | Eduardo I. Boemo,
Sergio López-Buedo,
Juan M. Meneses:
The Wave Pipeline Effect on LUT-Based FPGA Architectures.
FPGA 1996: 45-50 |
| 1995 |
|---|
| 1 | | Eduardo I. Boemo,
Guillermo González de Rivera,
Sergio López-Buedo,
Juan M. Meneses:
Some Notes on Power Management on FPGA-Based Systems.
FPL 1995: 149-157 |
