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T. Sansaloni

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2008
8EEF. Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre: Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. Signal Processing Systems 52(1): 35-44 (2008)
7EEF. Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls: Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. Signal Processing Systems 52(2): 181-191 (2008)
2007
6EET. Sansaloni, A. Perez-Pascual, V. Torres, Javier Valls: Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. VLSI Signal Processing 47(2): 183-187 (2007)
2005
5 F. Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls: Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. FPL 2005: 535-538
2003
4EEJ. Marí-Roig, V. Torres, Ma José Canet, A. Pérez, T. Sansaloni, Francisco Cardells-Tormo, F. Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat: DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. FPL 2003: 988-991
3EET. Sansaloni, Javier Valls, Keshab K. Parhi: Digit-Serial Complex-Number Multipliers on FPGAs. VLSI Signal Processing 33(1-2): 105-115 (2003)
2002
2EEA. Perez-Pascual, T. Sansaloni, Javier Valls: FPGA-based radix-4 butterflies for HIPERLAN/2. ISCAS (3) 2002: 277-280
1999
1EEJavier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo: Fast FPGA-based pipelined digit-serial/parallel multipliers. ISCAS (1) 1999: 482-485

Coauthor Index

1Vicenc Almenar-Terre [4] [8]
2F. Angarita [4] [5] [7] [8]
3Eduardo I. Boemo [1]
4Ma José Canet [4] [7] [8]
5Francisco Cardells-Tormo [4]
6J. Marí-Roig [4]
7Keshab K. Parhi [3]
8M. M. Peiro [1]
9A. Pérez [4]
10A. Perez-Pascual [2] [5] [6] [7]
11V. Torres [4] [6]
12Javier Valls [1] [2] [3] [5] [6] [7] [8]
13Javier Valls-Coquillat [4]
14Felip Vicedo [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)