| 2006 |
|---|
| 7 | EE | Francisco-Javier Veredas,
Michael Scheppler,
Hans-Jörg Pfleiderer:
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.
DATE Designers' Forum 2006: 36-41 |
| 6 | EE | Francisco-Javier Veredas,
Hans-Jörg Pfleiderer:
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.
FPL 2006: 1-2 |
| 5 | EE | Francisco-Javier Veredas,
Michael Scheppler,
Bumei Zhai,
Hans-Jörg Pfleiderer:
LUT-based MPGAs for fast turnaround time conversion flow.
ISCAS 2006 |
| 4 | EE | Francisco-Javier Veredas,
Michael Scheppler,
Bumei Zhai,
Hans-Jörg Pfleiderer:
Regular Routing Architecture for a LUT-based MPGA.
ISVLSI 2006: 257-262 |
| 2005 |
|---|
| 3 | | Francisco-Javier Veredas,
Michael Scheppler,
Will Moffat,
Bingfeng Mei:
Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.
FPL 2005: 106-111 |
| 2 | | Bingfeng Mei,
Francisco-Javier Veredas,
Bart Masschelein:
Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.
FPL 2005: 622-625 |
| 1 | EE | Francisco-Javier Veredas,
Jordi Carrabina:
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.
PATMOS 2005: 666-673 |
