| 2004 |
|---|
| 5 | EE | Debesh Kumar Das,
Tomoo Inoue,
Susanta Chakraborty,
Hideo Fujiwara:
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity.
Asian Test Symposium 2004: 342-347 |
| 1999 |
|---|
| 4 | EE | Susanta Chakraborty,
Sandip Das,
Debesh K. Das,
Bhargab B. Bhattacharya:
Synthesis of Symmetric Functions for Path-Delay Fault Testability.
VLSI Design 1999: 512-517 |
| 1998 |
|---|
| 3 | | Debesh K. Das,
Susanta Chakraborty,
Bhargab B. Bhattacharya:
Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits.
ASP-DAC 1998: 469-474 |
| 1997 |
|---|
| 2 | EE | Debesh Kumar Das,
Susanta Chakraborty,
Bhargab B. Bhattacharya:
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.
VLSI Design 1997: 303-309 |
| 1993 |
|---|
| 1 | EE | Susanta Chakraborty,
Debesh Kumar Das,
Bhargab B. Bhattacharya:
Logical redundancies in irredundant combinational circuits.
J. Electronic Testing 4(2): 125-130 (1993) |
