Víctor H. Champac Vilela
List of publications from the
2008 |
22 | EE | Daniel Iparraguirre-Cardenas,
Jose Luis Garcia-Gervacio,
Víctor H. Champac:
A design methodology for logic paths tolerant to local intra-die variations.
ISCAS 2008: 596-599 |
21 | EE | Nestor Hernandez,
Víctor H. Champac:
Testing Skew and Logic Faults in SoC Interconnects.
ISVLSI 2008: 151-156 |
20 | EE | Roberto Gómez,
Alejandro Girón,
Víctor H. Champac:
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.
J. Electronic Testing 24(6): 529-538 (2008) |
2007 |
19 | EE | Antonio Zenteno Ramirez,
Guillermo Espinosa,
Víctor H. Champac:
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.
IEEE Trans. VLSI Syst. 15(5): 572-577 (2007) |
2005 |
18 | EE | Roberto Gómez,
Alejandro Girón,
Víctor H. Champac:
Test of Interconnection Opens Considering Coupling Signals.
DFT 2005: 247-258 |
2004 |
17 | EE | Antonio Zenteno,
Víctor H. Champac,
Michel Renovell,
Florence Azaïs:
Analysis and Attenuation Proposal in Ground Bounce.
Asian Test Symposium 2004: 460-463 |
16 | | Fernando Mendoza-Hernandez,
Mónico Linares Aranda,
Víctor H. Champac Vilela:
An improved technique to increase noise-tolerance in dynamic digital circuits.
ISCAS (2) 2004: 489-492 |
15 | | Fernando Mendoza-Hernandez,
Mónico Linares Aranda,
Víctor H. Champac Vilela:
The noise immunity of dynamic digital circuits with technology scaling.
ISCAS (2) 2004: 493-496 |
14 | EE | Fabian Vargas,
Víctor H. Champac:
Guest Editorial.
J. Electronic Testing 20(4): 331-332 (2004) |
2003 |
13 | EE | Víctor H. Champac,
Ingrid Jansch-Pôrto:
Guest Editorial.
J. Electronic Testing 19(1): 11 (2003) |
2002 |
12 | EE | Fernando Mendoza-Hernandez,
M. Linares,
Víctor H. Champac,
A. Diaz-Sanchez:
A new technique for noise-tolerant pipelined dynamic digital circuits.
ISCAS (4) 2002: 185-188 |
2001 |
11 | EE | Antonio Zenteno,
Víctor H. Champac:
Resistive Opens in a Class of CMOS Latches: Analysis and DFT.
VTS 2001: 138-144 |
10 | EE | Marcelo Lubaszewski,
Víctor H. Champac:
Guest Editorial.
J. Electronic Testing 17(2): 83-84 (2001) |
9 | EE | Antonio Zenteno,
Víctor H. Champac,
Joan Figueras:
Detectability Conditions of Full Opens in the Interconnections.
J. Electronic Testing 17(2): 85-95 (2001) |
2000 |
8 | EE | Víctor H. Champac,
Antonio Zenteno:
Detectability Conditions for Interconnection Open Defect.
VTS 2000: 305-312 |
1999 |
7 | EE | Víctor H. Champac,
José Castillejos,
Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs.
J. Electronic Testing 15(1-2): 53-62 (1999) |
1998 |
6 | EE | Víctor H. Champac,
José Castillejos,
Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs.
VTS 1998: 106-111 |
1995 |
5 | EE | Víctor H. Champac,
Joan Figueras:
Testability of floating gate defects in sequential circuits.
VTS 1995: 202-207 |
1994 |
4 | EE | Víctor H. Champac,
Antonio Rubio,
Joan Figueras:
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 359-369 (1994) |
1993 |
3 | | Víctor H. Champac,
Antonio Rubio,
Joan Figueras:
Analysis of the Floating Gate Defect in CMOS.
DFT 1993: 101-108 |
1992 |
2 | EE | J. A. Segura,
Víctor H. Champac,
Rosa Rodríguez-Montañés,
Joan Figueras,
J. A. Rubio:
Quiescent current analysis and experimentation of defective CMOS circuits.
J. Electronic Testing 3(4): 337-348 (1992) |
1991 |
1 | | Rosa Rodríguez-Montañés,
J. A. Segura,
Víctor H. Champac,
Joan Figueras,
J. A. Rubio:
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.
ITC 1991: 510-519 |