| |
| 2008 | ||
|---|---|---|
| 5 | EE | Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song: A Cost Effective BIST Second-Order Sigma-Delta-Modulator. DDECS 2008: 314-319 |
| 2007 | ||
| 4 | EE | Hao-Chiao Hong: A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators. IEEE Trans. VLSI Syst. 15(12): 1341-1350 (2007) |
| 3 | EE | Hao-Chiao Hong: A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators. J. Electronic Testing 23(6): 527-538 (2007) |
| 2004 | ||
| 2 | EE | Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng: A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. Asian Test Symposium 2004: 62-67 |
| 2002 | ||
| 1 | EE | Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu: On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium 2002: 49- |
| 1 | Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) | [1] [2] |
| 2 | Jiun-Lang Huang | [1] |
| 3 | Sheng-Chuan Liang | [5] |
| 4 | Hong-Chin Song | [5] |
| 5 | Cheng-Wen Wu | [1] [2] |