| 2006 |
|---|
| 8 | EE | Jia Di,
D. P. Vasudevan:
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.
DELTA 2006: 149-156 |
| 2005 |
|---|
| 7 | EE | D. P. Vasudevan,
Parag K. Lala:
A Technique for Modular Design of Self-Checking Carry-Select Adder.
DFT 2005: 325-333 |
| 6 | EE | Jia Di,
Parag K. Lala,
D. P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.
DFT 2005: 371-379 |
| 5 | EE | D. P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
CMOS Realization of Online Testable Reversible Logic Gates.
ISVLSI 2005: 309-310 |
| 2004 |
|---|
| 4 | EE | D. P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
A Novel Approach for On-line Testable Reversible Logic Circuit Desig.
Asian Test Symposium 2004: 325-330 |
| 3 | | D. P. Vasudevan,
James Patrick Parkerson,
Parag K. Lala:
Logic implementation using a reversible gate.
Circuits, Signals, and Systems 2004: 452-456 |
| 2 | EE | D. P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks.
DFT 2004: 324-331 |
| 1 | | D. P. Vasudevan,
Parag K. Lala:
A New Reversible Logic Gate and its Applications.
ESA/VLSI 2004: 480-484 |
