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2005 | ||
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3 | EE | Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst. 13(12): 1384-1393 (2005) |
2004 | ||
2 | EE | Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23 |
1 | EE | Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673 |
1 | John Bainbridge | [2] [3] |
2 | Aristides Efthymiou | [1] [2] [3] |
3 | Christos P. Sotiriou | [1] |